Semiconductor Package Vertical Stacking for Wearable Devices
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Solution Overview
Problem
Wearable electronic devices face increased size and weight issues due to the integration of additional components like GPS and heart rate sensing modules, affecting user experience.
Innovation Solution
A semiconductor device package is designed with a substrate, a dielectric layer, a thin film transistor (TFT), and electronic components, where the dielectric layer's surface roughness is reduced to accommodate these components without increasing the package's size and weight, using a method that includes forming a buffer layer, TFT layer, and electronic components on opposite surfaces of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional electronic components (GPS module, heart rate sensing module) are integrated into the housing, then the functionality and versatility of the wearable device are improved, but the size and weight of the housing increase
Solution Approach 1:
The patent transitions from planar component arrangement to three-dimensional vertical stacking. Multiple components (TFT layer, dielectric layers, electronic components) are arranged in different vertical levels, utilizing the Z-dimension to accommodate more functionality without increasing the horizontal footprint, thus preventing weight increase while maintaining versatility
2Adaptability or versatility
If additional electronic components are integrated into the housing, then the functionality of the wearable device is improved, but the size of the housing increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange components in three dimensions rather than spreading them out in two dimensions. The TFT layer, dielectric layers, and electronic components are positioned at different vertical levels, effectively using the Z-dimension to pack more functionality into the same horizontal footprint, thereby increasing versatility without enlarging the overall device size
3Ease of manufacture
If a rough substrate surface is used, then the manufacturing process is simpler, but the TFT layer formation and component integration become difficult
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the rough substrate and the TFT layer. This dielectric layer serves as a mediator that provides a flat, controlled surface for precise TFT formation and component integration, while the underlying rough substrate maintains its manufacturing simplicity. The dielectric layer decouples the substrate preparation ease from the subsequent precision requirements
Data Source
AI summary
A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.