Semiconductor Package with Step-Shaped Die Pad and Conductive Clip

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving a high package size to chip ratio, which is essential for maximizing performance, especially in power switching applications, due to design limitations that make it difficult to exceed a ratio of 0.5.

Innovation Solution

A semiconductor package design featuring a dual-gauge die pad with a step-shaped profile and a conductive clip that wraps around the die pad, allowing the semiconductor die to be mounted close to the edge of the encapsulant, thereby increasing the package size to chip ratio beyond 0.5.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a conventional lead frame style package with die paddle and plurality of leads is used, then the package structure is simple and easy to manufacture, but the package size to chip ratio is limited to less than 0.5

Engineering Contradiction:

Improvepackage structure simplicityVSAvoidpackage size to chip ratio

Core Design Contradiction:

Ease of manufactureVSArea of moving object

Solution Approach 1:

The patent transitions from a conventional planar lead frame structure to a three-dimensional configuration where the die pad extends vertically with a top surface above the mold compound level. This dimensional change allows the die to be positioned closer to the package edge while maintaining structural integrity, achieving a package size to chip ratio greater than 0.5

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The die pad is embedded within the mold compound body, with the top surface of the die pad extending above the mold compound level. The semiconductor die is mounted on this exposed top surface, creating a nested configuration that maximizes space utilization and enables higher package size to chip ratios

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of moving object

If the semiconductor die is positioned close to the edge of the mold compound body, then the package size to chip ratio increases, but the structural support and electrical connection become difficult to maintain

Engineering Contradiction:

Improvepackage size to chip ratioVSAvoidstructural support and electrical connection

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The die pad is designed with different surface levels: a top surface above the mold compound level for die mounting, and a bottom surface at or below the mold compound level for structural support and electrical connection. This local differentiation allows the die to be positioned at the edge while maintaining both structural integrity and electrical connectivity

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11069600B2Semiconductor package with space efficient lead and die pad design

Publication Date: 2021.07.20 INFINEON TECHNOLOGIES AG

AI summary

A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.