Symmetrical Semiconductor Package Layout for Low Stray Inductance
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Solution Overview
Problem
Semiconductor power transistor devices face limitations due to parasitic inductances in electrical connections, leading to voltage drops and performance issues, especially at high load currents and voltages, which are exacerbated by high electric fields in power device operations.
Innovation Solution
A semiconductor package design featuring a semiconductor transistor die with symmetrical electrical connectors on opposing lateral sides, extending through an encapsulant, to reduce parasitic inductances and ensure even current distribution, thereby minimizing voltage drops and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If electrical connectors are arranged asymmetrically or in a conventional manner, then the device complexity is reduced, but parasitic inductances increase leading to voltage drops and performance limitations
Solution Approach 1:
The patent applies asymmetry by using a symmetrical arrangement of electrical connectors (specifically two connectors positioned symmetrically on opposite sides of the semiconductor die) to counteract the asymmetrical current flow patterns that occur during device operation. This symmetrical geometry creates balanced current distribution paths that reduce the net parasitic inductance effect, directly addressing the harmful factor of voltage drops during high di/dt events.
Solution Approach 2:
The patent moves the electrical connectors from a conventional single-plane arrangement to a three-dimensional configuration where connectors extend through the encapsulant in opposite directions. This dimensional change allows current to flow through multiple spatial paths simultaneously, effectively reducing the loop area and associated parasitic inductance while maintaining electrical connectivity.
2Power
If high load currents are used to meet power requirements, then the power delivery is improved, but voltage drops due to parasitic inductances increase
Solution Approach 1:
The patent segments the current path into multiple parallel conductive paths by using multiple electrical connectors (at least two) that are symmetrically arranged. This segmentation allows the total current to be distributed across multiple connectors simultaneously, reducing the current density in each individual connector and thereby reducing the I²R losses and voltage drops associated with parasitic inductances.
Solution Approach 2:
The patent changes the geometric parameters of the electrical connection system by extending connectors through the encapsulant in opposite directions and positioning them symmetrically. This parameter change optimizes the current distribution characteristics and reduces the effective parasitic inductance, enabling high power delivery with minimized voltage drops during high di/dt transients.
3Reliability
If discrete semiconductor packages are embedded in printed circuit boards, then high electric field reliability is improved, but parasitic inductances in electrical connections remain significant
Solution Approach 1:
The patent inverts the conventional connector arrangement by extending electrical connectors through the encapsulant in opposite directions rather than having them all emerge from the same side. This inverted configuration creates symmetrical current paths that cancel out parasitic inductance effects, maintaining the high electric field reliability of discrete packages while eliminating the connection inductance problem.
Data Source
AI summary
A semiconductor package includes: a semiconductor transistor die having an emitter/source contact pad, a drain/collector contact pad, and a gate contact pad; at least two electrical connectors disposed in a symmetrical manner on opposing lateral sides of the semiconductor die and connected with at least one of the contact pads; and an encapsulant embedding the semiconductor transistor die. The two or more electrical connectors extend through the encapsulant and form protruding sections above an upper surface of the encapsulant.