Semiconductor Package Structure With Stress-Buffer Holes
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Solution Overview
Problem
Semiconductor packages face reliability issues due to thermal stress caused by mismatched coefficients of thermal expansion (CTEs) between substrate and semiconductor die materials, leading to warping or cracking and potential damage to electrical connections, especially in larger packages.
Innovation Solution
The semiconductor package structure incorporates holes formed on the substrate surface, which can be filled with a stress buffer layer, and a polymer material under the semiconductor dies, along with a frame and buffer layer to manage thermal expansion and reduce stress, thereby preventing warping and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor packages use different materials for substrate and semiconductor die, then electrical connection and functionality are achieved, but thermal stress causes warping or cracking leading to damaged electrical connections
Solution Approach 1:
The patent introduces holes with specific geometric parameters (size, depth, distribution) into the substrate to modify its thermal and mechanical properties. By changing the physical structure parameters of the substrate, the package can accommodate thermal expansion differences between materials while maintaining electrical connection reliability.
Solution Approach 2:
The patent employs a porous substrate structure with holes formed therein. This porous configuration allows the substrate to better absorb and distribute thermal stress, preventing warping and cracking that would otherwise damage electrical connections. The holes create compliance in the substrate structure to handle differential thermal expansion.
2Area of stationary object
If larger package sizes are used, then more electrical connections and higher power handling are achieved, but thermal stress and warping increase significantly
Solution Approach 1:
The patent modifies the substrate structure by introducing holes with varying parameters (size, depth, spacing) that scale appropriately with package size. This allows larger packages to maintain structural integrity by distributing thermal stress across the expanded area through the porous structure.
Solution Approach 2:
The patent divides the continuous substrate structure into segmented regions separated by holes. This segmentation allows different parts of the large package to expand and contract independently, reducing overall warping and maintaining reliability across the entire large package area.
3Ease of manufacture
If traditional solid substrate structure is used, then manufacturing simplicity is maintained, but thermal stress management is insufficient leading to warping and cracking
Solution Approach 1:
The patent transitions from a solid substrate to a porous substrate with holes. While this adds structural complexity, the holes can be formed using standard semiconductor manufacturing techniques like photolithography and etching, maintaining reasonable manufacturing ease while dramatically improving resistance to warping and cracking.
Solution Approach 2:
The patent optimizes the geometric parameters of the holes (size, spacing, depth, pattern) to achieve the desired balance between manufacturing feasibility and mechanical strength. By carefully selecting these parameters, the substrate gains warping resistance while remaining compatible with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of electrical connection damage and enhances the reliability and lifespan of semiconductor packages by mitigating thermal stress, improving thermal dissipation, and maintaining the integrity of the semiconductor package structure.
Implementation Method 1
The semiconductor package may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the various substrate and semiconductor die materials
Implementation Method 2
improving thermal dissipation
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.