Semiconductor Package Layout for Stress Balance and Coplanarity
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Solution Overview
Problem
Existing semiconductor packages face issues with stress imbalance and poor coplanarity due to the presence of dummy silicon dies, which affect their performance and reliability.
Innovation Solution
The semiconductor package design includes additional semiconductor structures arranged adjacent to corners or edges of the interposer and substrate, with some structures acting as dummy packages to balance stress and improve coplanarity, featuring encapsulated semiconductor dies and redistribution structures with conductive pillars and underfill materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy silicon dies are placed over the interposer, then the semiconductor package structure is completed, but stress imbalance and poor coplanarity occur
Solution Approach 1:
The patent applies local quality by configuring dummy semiconductor structures with specific properties at particular locations (corners and edges of the interposer) to address stress imbalance locally. These dummy structures are designed with specific dimensions, materials, and orientations to compensate for stress in their local regions without requiring changes to the entire package structure.
Solution Approach 2:
The patent implements the counterweight principle by placing dummy semiconductor structures at strategic locations to balance the stress distribution across the interposer. These dummy structures act as counterweights that offset the stress imbalances created by the asymmetric arrangement of functional semiconductor devices, thereby improving overall coplanarity and reducing warpage.
2Productivity
If multiple semiconductor dies are integrated within the same package, then manufacturing cost is reduced and density is increased, but stress imbalance and poor coplanarity occur
Solution Approach 1:
The patent applies local quality by configuring dummy semiconductor structures with specific properties at particular locations (corners and edges of the interposer) to address stress imbalance locally. These dummy structures are designed with specific dimensions, materials, and orientations to compensate for stress in their local regions without requiring changes to the entire package structure.
Solution Approach 2:
The patent addresses the asymmetric stress distribution caused by heterogeneous integration by introducing asymmetric dummy structures at specific locations. The dummy structures are positioned and dimensioned asymmetrically to counterbalance the inherent asymmetry in the functional device layout, thereby achieving stress equilibrium and improved coplanarity.
Data Source
AI summary
A semiconductor package includes an interposer over a substrate that includes interconnect traces, a redistribution structure on the interposer, a first semiconductor structure, a second semiconductor structure and a third semiconductor structure on the redistribution structure. The first semiconductor structure includes a first semiconductor die and a first encapsulant that encapsulates the first semiconductor die. The second semiconductor structure includes a second semiconductor die and a second encapsulant that encapsulates the second semiconductor die. The third semiconductor structure is disposed adjacent to a corner or an edge of the substrate in a top plan view of the substrate. The third semiconductor structure includes a third semiconductor die and a third encapsulant that encapsulates the third semiconductor die. The third semiconductor structure is electrically insulated from the substrate, the first semiconductor structure and the second semiconductor structure.