Semiconductor Package Locking Structure for Thermal Stress Equalization

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Solution Overview

Problem

Semiconductor devices face challenges with high electrical loads causing detrimental heating and interface connection failures due to uneven thermal stress, leading to reduced performance and lifespan.

Innovation Solution

The implementation of a semiconductor package with a dual-sided heat dissipation structure, including a heat spreader, die clip, and lead frame with pre-assembled connection points, and the use of interstitial conductors to manage thermal stresses and simplify manufacturing by reducing the number of assembly steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dual-sided heat dissipation structure is implemented, then thermal stress management is improved, but device complexity increases

Engineering Contradiction:
Improvethermal stress managementVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The lead frame is divided into multiple segments including a first lead frame portion and a second lead frame portion positioned on opposite sides of the semiconductor die. Each portion independently manages thermal stress in its respective direction, allowing the structure to handle multi-directional thermal expansion without requiring a completely redundant dual-sided architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The lead frame portions serve multiple functions: they provide electrical connections to the semiconductor die terminals and simultaneously act as thermal stress management structures. This multi-functionality reduces the need for separate components, thereby managing complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple assembly steps are used to ensure precise alignment, then manufacturing precision is improved, but productivity decreases

Engineering Contradiction:
Improvealignment precisionVSAvoidassembly efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The lead frame portions are pre-formed with specific geometries and connection configurations before assembly. The first lead frame portion is预先 configured to connect to first terminals, and the second lead frame portion is pre-configured for second terminals, eliminating the need for complex realignment operations during the assembly process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention combines multiple functions into integrated components: the lead frame portions simultaneously provide electrical connectivity, mechanical support, and thermal stress management. This merging reduces the number of separate assembly steps required compared to using separate components for each function.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively manages thermal stresses and improves assembly efficiency, reducing the risk of connection failures and extending the lifespan of semiconductor devices by evenly distributing thermal expansion and contraction.

Implementation Method 1

a heat spreader on the first side of the semiconductor die

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

uneven thermal stress, such as uneven thermal expansion or contraction across the components of the semiconductor devices

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250006602A1Semiconductor package with directional locking structure
Publication Date: 2025.01.02 SPINERGY INC
  • US20250006602A1 patent drawing
  • US20250006602A1 patent drawing
  • US20250006602A1 patent drawing

AI summary

The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, molding material, and a conductive structure. The conductive structure is at least partly stacked with the semiconductor die, and the conductive structure includes a plurality of slots positioned around a point of the semiconductor die. The plurality of slots is configured to equalize thermal stresses during the operation of the semiconductor die about the point of the semiconductor die, where the thermal stresses are associated with coefficient of thermal expansion mismatches between the conductive structure and the molding material. In addition, at least a portion of the molding material is in contact with the conductive structure.