Semiconductor Package Stress Reduction via Layered Protection

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Solution Overview

Problem

Semiconductor packages face reliability issues due to stress applied to semiconductor chips during physical and electrical connection to circuit substrates, which can lead to cracks in the redistribution layer and mechanical or thermal shock.

Innovation Solution

A semiconductor package design featuring a layered structure with specific protection layers and a barrier layer, where the modulus of elasticity of the second protection layer is greater than that of the third protection layer, and the post layer's width is equal to or less than the barrier layer's width, reducing stress on the chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder balls are used to electrically connect semiconductor chip to circuit substrate, then electrical connection is achieved, but stress is applied to semiconductor chip causing cracks in redistribution layer

Engineering Contradiction:

Improvereliability of semiconductor packageVSAvoidstress resistance of semiconductor chip

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent divides the connection structure into multiple segments: semiconductor chip, first protection layer, redistribution layer, second protection layer, and solder ball portion. This segmentation isolates the semiconductor chip from direct stress exposure by distributing the mechanical load across multiple layers, particularly through the compliant second protection layer that absorbs thermal and mechanical stress.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second protection layer acts as an intermediary between the rigid solder ball portion and the semiconductor chip. This intermediate layer has different mechanical properties (different modulus of elasticity) that allow it to absorb and distribute stress, preventing direct transmission of mechanical and thermal stress to the chip and redistribution layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If direct connection between chip and substrate is made, then electrical connection is achieved, but mechanical shock and thermal shock damage the chip

Engineering Contradiction:

Improvedurability of semiconductor packageVSAvoidmechanical and thermal stress on chip

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The second protection layer is designed with specific mechanical properties (different modulus of elasticity compared to surrounding layers) to provide beforehand cushioning against mechanical and thermal shock. This layer absorbs and dissipates stress energy before it can reach the semiconductor chip, protecting it from damage during connection and operation.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent employs composite material structure with multiple protection layers having different material properties. The second protection layer uses a material with different modulus of elasticity to create a composite structure that combines the electrical connectivity function with mechanical stress absorption and thermal shock resistance.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS11557560B2Semiconductor package for improving reliability

Publication Date: 2023.01.17 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.