Semiconductor Package Stress Relief via Segmented Interconnects

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing warping and cracking in package structures due to the integration of multiple interconnects and integrated circuit dies, which affects the reliability and performance of semiconductor devices, particularly in miniaturized packaging applications like Package-on-Package (PoP) technology.

Innovation Solution

The formation of multiple interconnect structures with conductive pillars and redistribution structures over these interconnects, which reduces stress and warping through planarization and improved electrical routing, enhancing the bonding between devices and package components, and utilizing different materials and techniques for finer line features in redistribution layers to improve electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple interconnect structures and integrated circuit dies are integrated into a package structure, then the integration density and functionality are improved, but warping and cracking occur affecting reliability

Engineering Contradiction:
Improveintegration densityVSAvoidpackage structure reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The package structure is divided into multiple separate interconnect structures (first interconnect structure and second interconnect structure) that are laterally adjacent, allowing independent stress management for each segment while maintaining overall integration density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the package structure are provided with different properties - the underfill material specifically extends between interconnect structures to provide localized stress relief, while conductive pillars provide localized electrical connection, allowing each region to address specific requirements

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If more interconnect structures are integrated, then electrical routing capability is improved, but stress and warping increase

Engineering Contradiction:
Improveelectrical routing capabilityVSAvoidstructural stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The underfill material acts as an intermediary substance that extends between adjacent interconnect structures, providing mechanical support and stress distribution that prevents warping while allowing multiple interconnect structures to be integrated for enhanced electrical routing

Inventive Principle:
Principle #24Intermediary (Mediator)

3Volume of moving object

If miniaturization is pursued for smaller packages, then device size is reduced, but warping and cracking risks increase

Engineering Contradiction:
Improvepackage sizeVSAvoidjoint reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The package structure employs a nested arrangement where multiple interconnect structures are laterally adjacent and stacked in layers, with underfill material nested between them, allowing compact miniaturization while the nested underfill provides continuous stress relief throughout the structure

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11664350B2Semiconductor device and method of manufacture
Publication Date: 2023.05.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11664350B2 patent drawing
  • US11664350B2 patent drawing
  • US11664350B2 patent drawing

AI summary

A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.