Semiconductor Package Vertical Stack Stress-Relief Structure
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Solution Overview
Problem
The integration density of semiconductor devices is limited by fabrication process challenges, making it difficult to achieve highly integrated semiconductor devices with high speed and high functionality.
Innovation Solution
A semiconductor package with vertically stacked semiconductor chips and a stress-relieving structure made of materials like epoxy resin, polyimide, or silicone is used to relieve stress between the chips, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked semiconductor chips are used to increase integration density, then the integration density and functionality are improved, but stress between chips causes reliability deterioration
Solution Approach 1:
A stress-relieving structure is introduced as an intermediary element between adjacent semiconductor chips in the vertical stack. This structure absorbs and distributes the thermal expansion stress and mechanical stress generated during operation and packaging, preventing stress-induced cracking and delamination at the chip interfaces, thereby maintaining high reliability while enabling increased integration density through vertical stacking
Solution Approach 2:
The stress-relieving structure modifies the mechanical and thermal parameters of the chip stack by providing a compliant interface that accommodates differential thermal expansion coefficients between chips and packaging materials. This parameter adjustment allows the system to withstand thermal cycling and mechanical loading without failure, enabling reliable operation of high-density vertically stacked configurations
2Productivity
If more semiconductor chips are vertically stacked to achieve high speed and multi-functionality, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The stress-relieving structure is divided into multiple discrete elements or patterns that can be independently formed and positioned between different chip stacks. This segmentation allows the complex stress management function to be achieved through modular, repeatable fabrication steps rather than requiring entirely new complex processes, thereby enabling high-performance multi-chip stacks with manageable fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress-relieving structure improves the reliability of the semiconductor package by reducing stress-induced cracking and failure, enabling higher integration density and faster performance.
Implementation Method 1
a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.