3D Semiconductor Package Structural Member Warpage Control

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Solution Overview

Problem

The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional integrated circuits, prompting the exploration of three-dimensional ICs, but existing 3D IC formation processes face challenges in achieving efficient electrical connections and structural support during manufacturing.

Innovation Solution

The solution involves forming a semiconductor package with a first package and a second package bonded together using a structural member, such as a metal block or conductive balls, with additional support from a block or balls to reduce warpage and enhance connectivity, allowing for more efficient electrical interconnections and improved manufacturing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two dies are bonded together to form a 3D IC, then circuit density is increased, but structural stability and warpage control deteriorate

Engineering Contradiction:
Improvecircuit densityVSAvoidstructural stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

A carrier substrate is introduced as an intermediary component between the first and second dies. The carrier substrate provides a stable base that supports both dies, distributing mechanical stresses and preventing warpage. This mediator allows the stacked die configuration to achieve high circuit density while maintaining structural stability through its large surface area and mechanical properties.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If wire bonds are used to electrically connect dies to substrate, then electrical connectivity is achieved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The wire bonding process is extracted and replaced with a more straightforward bonding approach. Contact pads are directly formed on the carrier substrate, eliminating the need for separate wire bonding operations. This reduces manufacturing complexity by integrating the electrical connection function directly into the substrate fabrication process while maintaining reliable electrical connectivity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If more devices are integrated into one chip, then circuit density improves, but design complexity increases

Engineering Contradiction:
Improvecircuit densityVSAvoiddesign complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The integrated circuit is segmented into multiple separate dies that are stacked vertically on a carrier substrate. This segmentation allows each die to be designed and manufactured independently with optimized functions, reducing the complexity of designing a single large chip while achieving high overall circuit density through the three-dimensional arrangement.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9293442B2Semiconductor package and method
Publication Date: 2016.03.22 PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
  • US9293442B2 patent drawing
  • US9293442B2 patent drawing
  • US9293442B2 patent drawing

AI summary

A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package.