Semiconductor Package Without Through-Holes
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Solution Overview
Problem
Conventional semiconductor packages face challenges in reducing size and thickness due to the structural weakening caused by through-holes, which also complicates the interconnection process and limits the miniaturization of the package.
Innovation Solution
A semiconductor package design featuring a dielectric layer with exposed traces and studs, eliminating the need for through-holes by using a conductive carrier with a dielectric layer that encapsulates the trace and stud layers, and surface finishings to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-holes are used to connect the substrate surfaces, then electrical connectivity is achieved, but the structural strength of the substrate is weakened
Solution Approach 1:
The patent extracts the through-hole from the substrate structure and replaces it with a surface-mounted pad configuration. The electrical connection is achieved through surface pads and conductive traces rather than penetrating through-holes, thereby maintaining substrate structural integrity while achieving the required electrical connectivity function.
Solution Approach 2:
The patent transitions from a three-dimensional through-hole penetration approach to a two-dimensional surface-mounted connection approach. Electrical connections are established through surface pads and traces on the substrate surface, eliminating the need for vertical through-hole pathways and preserving the substrate's structural strength.
2Strength
If through-holes are separated by large distances to maintain structural strength, then substrate strength is preserved, but the size of the semiconductor package increases
Solution Approach 1:
By removing the through-hole structure entirely and replacing it with surface-mounted pads, the patent eliminates the need to maintain large spacing between connection points. The surface pad configuration allows for compact layout while maintaining substrate structural integrity, thereby reducing the overall package size.
3Strength
If the substrate thickness is increased to avoid through-holes, then structural strength is maintained, but the thickness of the semiconductor package increases
Solution Approach 1:
The patent extracts the through-hole penetration concept and replaces it with surface-mounted electrical connections. This allows the substrate to maintain its original thickness without requiring increased thickness for structural support, as the surface pad configuration provides adequate mechanical strength while enabling compact package design.
4Ease of manufacture
If conventional substrate with through-holes is used, then manufacturing process is established, but device complexity increases due to interconnection requirements
Solution Approach 1:
The patent merges the electrical connection function into the substrate surface structure by integrating pads and traces directly onto the substrate surface. This consolidation eliminates the need for separate through-hole interconnection structures, reducing device complexity while maintaining ease of manufacture through established surface mounting techniques.
Data Source
AI summary
A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.