Semiconductor Package Sub-Substrate Interconnect
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to increased complexity and size from wire connections between memory and driving chips, leading to issues like wire sweeping, damage, and short-circuiting, as well as higher fabrication costs and defects.
Innovation Solution
A semiconductor package design featuring a novel structure with memory chips and a driving chip integrated on a single substrate, using a sub-substrate for direct electrical connections, eliminating the need for wire bonding and reducing package size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire connections are used to connect memory chips and driving chip, then electrical connection is achieved, but package size increases and reliability decreases due to wire sweeping, damage, and short-circuiting
Solution Approach 1:
The patent extracts and eliminates the wire connections from the package structure, replacing them with direct substrate-based electrical connections. This removes the source of wire-related defects (sweeping, damage, short-circuiting) while maintaining electrical connectivity between memory chips and driving chip through the substrate infrastructure.
Solution Approach 2:
The substrate serves as an intermediary structure that provides direct electrical connection paths between memory chips and the driving chip, eliminating the need for separate wire connections. The substrate's internal wiring and contact structures mediate the electrical connection, reducing complexity and improving reliability.
2Reliability
If wire loops are formed to prevent short-circuiting, then protection is provided, but package size increases
Solution Approach 1:
The patent removes the wire loops entirely from the package structure, replacing the short-circuit protection function with the substrate's inherent electrical isolation and routing design. This eliminates the area occupied by wire loops while maintaining protection against short-circuiting through proper substrate layout and insulation.
3Quantity of substance
If multiple memory chips are stacked to increase capacity, then memory capacity doubles, but wire length increases causing more defects
Solution Approach 1:
The patent transitions from vertical stacking with wire connections to a planar arrangement where multiple memory chips are mounted on the same substrate plane. This dimensional change allows direct substrate-based connections without requiring vertical wire routing, enabling increased memory capacity while maintaining connection reliability and reducing wire-related defects.
4Area of stationary object
If driving chip and memory chip are vertically stacked, then miniaturization is achieved, but signal transfer path grows in complexity
Solution Approach 1:
The patent segments the package into a planar configuration where the driving chip and memory chips are mounted separately on the substrate rather than vertically stacked. This segmentation allows for simpler, shorter signal paths on the substrate while achieving miniaturization through efficient use of the substrate area and reduced interconnection complexity.
Data Source
AI summary
A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.