Semiconductor Package With Connection Substrate Cavity
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compact size, low manufacturing cost, and efficient heat radiation while maintaining high electrical characteristics and thermal stability, particularly due to limitations in substrate design and redistribution of electrical connections.
Innovation Solution
A semiconductor package design featuring a lower substrate with a connection substrate having a cavity and conductive patterns, where the lower semiconductor chip is placed within the cavity and connected via bonding members, allowing for increased output terminals and redistribution of electrical circuits without an additional redistribution substrate, thereby reducing package thickness and enhancing heat radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional semiconductor package design is used with substrate and bonding wires, then electrical connections can be established, but the package size cannot be reduced further and manufacturing cost increases
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical stacking with chips positioned at different heights. The connection substrate creates multiple levels for mounting chips, allowing electrical connections in the vertical dimension rather than only horizontal plane, thus reducing overall package footprint while maintaining connectivity
Solution Approach 2:
The connection substrate with cavity structure allows one chip to be nested within the cavity while another chip is mounted on top, creating a nested configuration. This nesting approach maximizes space utilization and reduces package volume without requiring additional manufacturing complexity
2Adaptability or versatility
If additional redistribution substrate is added to increase output terminals, then electrical connection flexibility improves, but package thickness increases
Solution Approach 1:
The connection substrate serves multiple functions simultaneously: it provides mechanical support, creates the cavity for nesting chips, establishes electrical connections through conductive patterns, and enables redistribution of signals. This multi-functionality eliminates the need for separate redistribution substrates, reducing package thickness while maintaining electrical flexibility
Solution Approach 2:
The patent merges the functions of the substrate and redistribution layer into a single connection substrate structure. The conductive patterns are integrated directly into the connection substrate rather than requiring a separate redistribution substrate, thereby reducing the number of layers and overall package thickness
3Volume of moving object
If compact package design is implemented, then package size is reduced, but heat radiation becomes insufficient
Solution Approach 1:
The patent applies different material properties to different regions of the package. The connection substrate and chip substrates use materials with high thermal conductivity specifically in the regions where heat generation occurs, while other non-critical areas can use standard materials. This localized thermal management allows compact packaging while maintaining effective heat radiation from critical heat-generating components
Data Source
AI summary
A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.


