Semiconductor Package Substrate Design with Cavity and RDL Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3DIC packages have a large form factor, require complex heat dissipation features, and have costly interconnect structures like TSVs that result in long signal/power paths.
Innovation Solution
A semiconductor package design featuring a die stack with redistribution layers (RDLs) and connectors on one side, bonded to a package substrate with a cavity, allowing for a smaller form factor, reduced conduction paths, and independent heat dissipation features on opposite surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TSV interconnect structures are used in 3DIC packages, then electrical connection between dies is achieved, but manufacturing cost increases and conduction path length increases
Solution Approach 1:
The patent extracts the interconnect function from the substrate and relocates it to the die surface through redistribution layers (RDLs). This eliminates the need for costly TSVs in the substrate while maintaining electrical connectivity between dies and package components.
Solution Approach 2:
The patent transitions from vertical through-substrate interconnection (TSVs) to a combination of surface-level RDLs and side-wall connectors. This dimensional shift reduces conduction path length and manufacturing complexity while achieving the same electrical connection function.
2Reliability
If bonded die stack with package substrate is used, then electrical connection is achieved, but form factor increases
Solution Approach 1:
The patent moves interconnect structures from the substrate plane to the die surface and side-walls, utilizing three-dimensional space more efficiently. This reduces the horizontal footprint of the package while maintaining all necessary electrical connections.
Solution Approach 2:
The patent segments the interconnect function across multiple locations: RDLs on the die surface, connectors on side-walls, and corresponding pads on the package substrate. This distributed architecture reduces the required substrate area while maintaining connectivity.
3Reliability
If extensive TSVs are used for interconnection, then electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the complex TSV interconnect structure from the substrate and replaces it with simpler surface-level RDLs and side-wall connectors. This maintains electrical connection functionality while significantly reducing structural complexity and manufacturing difficulty.
4Reliability
If bonded die stack configuration is used, then electrical connection to top dies is achieved, but conduction path length increases
Solution Approach 1:
The patent shortens conduction paths by moving interconnect structures from deep within the substrate (TSVs) to the die surface and side-walls. This dimensional relocation reduces the physical length of signal and power paths while maintaining reliable electrical connection.
Data Source
AI summary
A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.