Semiconductor Package Structure With Connecting Substrate Cooling
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Solution Overview
Problem
Semiconductor packages face performance deterioration due to excessive heat generation during operation, as existing heat dissipation methods are inadequate.
Innovation Solution
A semiconductor package design featuring a package substrate with a lower semiconductor device, connecting substrate, and an upper semiconductor device, where the upper device is electrically connected through first and second through electrodes, and a heat dissipation member is used on the logic chip to enhance cooling, with wider electrodes and bumps for improved power supply and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are packaged in one semiconductor package, then system functionality is improved, but heat generation increases causing performance deterioration
Solution Approach 1:
The patent divides the semiconductor package into multiple functional layers including a lower semiconductor device layer, a connecting substrate layer, and an upper semiconductor device layer. This segmentation allows heat to be distributed across different layers and dissipation paths, preventing heat accumulation in a single location while maintaining system functionality.
Solution Approach 2:
The connecting substrate acts as an intermediary between the lower and upper semiconductor devices. It provides both electrical connection through through-electrodes and thermal management pathways, serving as a mediator that allows heat to be transferred from the upper device to the lower device and package substrate for dissipation.
2Ease of manufacture
If existing heat dissipation methods are used, then manufacturing simplicity is maintained, but heat dissipation effectiveness is inadequate
Solution Approach 1:
The patent merges electrical connection and thermal management functions into a single integrated structure. The through-electrodes in the connecting substrate simultaneously provide electrical connectivity between layers and thermal conduction pathways, eliminating the need for separate heat dissipation components and maintaining manufacturing simplicity while improving heat dissipation effectiveness.
3Reliability
If wider electrodes and bumps are used for improved power supply, then power supply stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the dimensional parameters of the through-electrodes and connection bumps, making them wider than conventional designs. This parameter change increases the cross-sectional area for both electrical current flow and thermal conduction, improving power supply stability and heat dissipation capability while the cost-effective formation process maintains manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively improves heat dissipation characteristics, stabilizes power supply to the logic chip, and reduces production costs by using a cost-effective process for forming wider electrodes and bumps, thereby enhancing the overall performance and reliability of the semiconductor package.
Implementation Method 1
a heat dissipation member on the logic chip
Data Source
AI summary
A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes. A plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device, and the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.