Semiconductor Package Substrate Hybrid Bump Technology
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Solution Overview
Problem
The existing semiconductor package systems require an additional process to form a dummy die for stacking memory chips, increasing production costs and reducing productivity due to the use of expensive silicon material and additional thickness, which complicates the manufacturing process.
Innovation Solution
A semiconductor package substrate is developed using copper pads and adhesive members formed through hybrid bump technology without the expensive dummy die, featuring a stack structure with different widths and protrusions to enhance adhesive strength and reliability, allowing for fine pitch and high standoff height without increasing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy die is formed between the semiconductor substrate and memory chip for stacking, then the memory chip can be attached and spaced from the substrate, but an additional manufacturing process is required and productivity is reduced
Solution Approach 1:
The invention extracts and eliminates the dummy die component from the package structure. Instead of using a separate dummy die to provide spacing and attachment functionality, the patent integrates these functions directly into the substrate structure through recessed regions and adhesive members, thereby removing the additional manufacturing process and improving productivity while maintaining attachment stability
Solution Approach 2:
The invention merges the spacing function and attachment function into the substrate itself. The recessed region in the substrate combines the spacing capability (previously provided by dummy die thickness) with the attachment capability (through adhesive members), eliminating the need for a separate dummy die component and simplifying the manufacturing process
2Reliability
If a silicon dummy die is used for stacking, then the memory chip can be mounted with proper spacing, but the cost of the entire package system is increased
Solution Approach 1:
The invention replaces the expensive silicon dummy die with a cost-effective substrate-integrated structure. The recessed region filled with adhesive member provides the necessary spacing function at a fraction of the cost of silicon dummy die, making the package system more economical while maintaining the required spacing for memory chip mounting
Solution Approach 2:
The substrate is designed to perform multiple functions: it provides mechanical support, electrical connections, and spacing (through the recessed region). This multi-functional design eliminates the need for a separate dummy die component, reducing material costs and simplifying the manufacturing process
3Reliability
If a silicon dummy die with predetermined thickness is used, then proper spacing is achieved, but the entire thickness of the package system is increased
Solution Approach 1:
The invention transitions from a three-dimensional dummy die structure to a two-dimensional recessed region in the substrate. By creating a recessed area in the substrate surface and filling it with adhesive member, the spacing function is achieved within the substrate plane rather than adding vertical thickness, thereby reducing the overall package thickness while maintaining proper spacing
Data Source
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AI summary
According to the embodiment, there is provided a semiconductor package substrate including an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating substrate, the protective layer covering the circuit pattern on the insulating substrate; a pad on the protective layer; and an adhesive member on the protective layer, wherein the pad includes a first pad buried in the protective layer, and a second pad on the first pad, the second pad protruding over the protective layer.