Stacked Semiconductor Package Substrate Region Segmentation
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Solution Overview
Problem
Conventional stacked semiconductor packages face challenges in achieving high-speed data processing due to differences in conductive wire lengths connecting semiconductor packages to a substrate, leading to inefficiencies in data transfer.
Innovation Solution
A semiconductor package design featuring a substrate with specific regions and connection patterns, including wiring lines and connection patterns that extend through the substrate, and conductive members like pins to connect these patterns across stacked packages, ensuring uniform electrical connectivity and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional conductive wires are used to connect semiconductor packages to substrate, then electrical connection is achieved, but data processing speed is limited due to varying wire lengths
Solution Approach 1:
The substrate is divided into multiple regions (first region, second region, third region) with connection patterns placed at different locations. This segmentation allows for optimized wiring paths that reduce length variations and improve signal integrity across different semiconductor packages.
Solution Approach 2:
Connection patterns are extended into the third region and routed through multiple layers/regions of the substrate rather than using simple planar connections. This dimensional approach allows for more uniform effective connection lengths despite physical stacking variations, thereby improving both speed and connection consistency.
2Productivity
If stacked semiconductor packages are used to increase data storage capacity and processing speed, then capacity and speed are improved, but varying conductive wire lengths cause processing inefficiencies
Solution Approach 1:
Different regions of the substrate are designed with specific connection patterns optimized for their local requirements. The first region accommodates the semiconductor chip, the second region provides transition connections, and the third region extends connections to minimize length variations. This localized optimization ensures uniform data transfer characteristics across all stacked packages.
Solution Approach 2:
The substrate acts as an intermediary structure with multiple regions and connection patterns that mediate between the stacked semiconductor packages. This intermediary design equalizes the effective connection lengths for all packages, eliminating the time variation in data transfer while maintaining high capacity and processing speed.
3Reliability
If connection patterns are placed on inner surfaces of substrate through through-holes, then electrical connectivity is improved, but substrate structure becomes more complex
Solution Approach 1:
The through-holes serving as connection patterns perform multiple functions: they provide electrical connectivity between layers, define the third region boundaries, and enable compact routing. This multi-functionality improves electrical connectivity while avoiding the need for separate complex structural elements.
Solution Approach 2:
Connection patterns are nested within the through-holes that pass through the substrate, with the third region effectively nested around the connection paths. This nested arrangement achieves complex electrical connectivity with minimal additional structural complexity, as the connection patterns utilize the existing through-hole geometry.
Data Source
AI summary
A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.