Semiconductor Package Substrate Ring Wiring for Electrolysis Plating
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Solution Overview
Problem
In semiconductor devices, particularly Ball Grid Array (BGA) with increasing pin count and miniaturization, it is challenging to arrange lead-out wiring for electrolysis plating due to crowded bonding electrodes and narrow pitch between land parts on the wiring substrate, leading to difficulties in extending the feeder to all land parts and potential issues like electric short circuits and moisture absorption.
Innovation Solution
The solution involves forming common wiring in the inner area of the bonding electrodes on the wiring substrate, allowing multiple lead-out wiring connections to the common wiring, which enables the feeder to reach all land parts for electrolysis plating, even in high-density areas, by using a ring-shaped common wiring and specific plating line configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bonding electrodes are arranged in multiple lines to increase pin count, then the number of bonding electrodes increases, but the wiring substrate size cannot be reduced and feeder arrangement becomes difficult
Solution Approach 1:
The patent transitions from planar feeder arrangement to three-dimensional feeder routing by allowing feeders to pass through the thickness direction of the wiring substrate. This enables feeders to reach land parts on the back surface without increasing the substrate's planar dimensions, resolving the contradiction between increasing bonding electrode count and maintaining compact substrate size.
Solution Approach 2:
The patent embeds feeders within the wiring substrate structure, routing them through internal pathways and via holes. This nesting approach allows feeders to be integrated into the substrate thickness rather than occupying external space, enabling high-density bonding electrode arrangements without proportionally increasing substrate size.
2Area of stationary object
If land parts are arranged in a lattice pattern with narrow pitch for miniaturization, then device size is reduced, but feeder passage becomes difficult
Solution Approach 1:
The patent utilizes the thickness dimension of the wiring substrate to route feeders, allowing them to bypass the narrow pitch constraints on the surface. By passing feeders through via holes and internal pathways, the system achieves miniaturized land part spacing without compromising feeder accessibility for electrolysis plating.
Solution Approach 2:
The patent introduces via holes as intermediary structures that connect the front surface bonding electrodes to the back surface land parts. These via holes serve as conduits for feeders, enabling electrolysis plating current to reach densely spaced land parts without requiring wide surface spacing.
3Manufacturing precision
If feeders are extended to all land parts for electrolysis plating, then plating coverage is complete, but electric short circuits and moisture absorption risks increase
Solution Approach 1:
The patent divides the common wiring into multiple separate lead-out wirings that are spatially separated as they extend to different land parts. This segmentation reduces the risk of electric short circuits between feeders while maintaining complete plating coverage across all land parts including those at the substrate edges.
Solution Approach 2:
The patent applies insulating films (such as solder resist) over the feeders and wiring structures to provide electrical insulation and moisture protection. This thin film barrier prevents electric short circuits and moisture absorption while allowing the feeders to maintain their routing paths for complete plating coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective electrolysis plating on all land parts, increasing pin count and enabling miniaturization of semiconductor devices while preventing issues like electric shorts and moisture absorption by ensuring proper electrical supply and insulation.
Implementation Method 1
Plating consists of each film of nickel and gold, for example. As the method of plating formation, the electrolysis plating method and the electroless plating method are mainly known.
Data Source
AI summary
Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected to common wiring 3p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3a of package substrate 3, and the back surface.