Semiconductor Package Support Structure for POP Thickness Uniformity
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Solution Overview
Problem
Existing package-on-package (POP) technology faces challenges in achieving thickness uniformity and stability due to warpage and void formation during the manufacturing process of semiconductor packages.
Innovation Solution
The introduction of support members on the upper substrate and adhesive members bonding these to the semiconductor chip's surface, along with an encapsulant filling the space between the substrates, ensures uniform thickness and prevents void formation and warpage by maintaining a consistent joint pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If package-on-package (POP) technology is used to achieve high performance and miniaturization, then vertical stacking of semiconductor packages is enabled, but thickness uniformity becomes difficult to secure
Solution Approach 1:
The invention introduces support members at specific locations on the upper substrate to provide localized thickness control. These support members are positioned at critical areas where thickness variation occurs, allowing local adjustment and compensation without affecting the entire package structure.
Solution Approach 2:
The support members act as intermediary elements between the upper substrate and the encapsulant. They mediate the thickness control by providing a physical reference structure that the encapsulant flows around, ensuring uniform thickness distribution across the package while enabling vertical stacking.
2Manufacturing precision
If support members are added to control thickness, then thickness uniformity is improved, but device complexity increases
Solution Approach 1:
The thickness control function is segmented into discrete support members rather than requiring a complex overall structure. Each support member is a simple, independent element that can be easily manufactured and positioned, reducing the complexity of the entire device while achieving the desired precision.
Solution Approach 2:
The support members are designed as simple, easily manufacturable components that can be disposed of or integrated into the final package. Their simplicity allows for cost-effective production and positioning, offsetting the increased structural complexity by using inexpensive, straightforward elements.
3Reliability
If adhesive members are used to bond support members to the semiconductor chip, then void formation is prevented, but manufacturing process complexity increases
Solution Approach 1:
The adhesive members are applied in advance to the support members or semiconductor chip surfaces before the bonding step. This preliminary action ensures proper adhesion and prevents void formation by establishing the bonding interface beforehand, making the subsequent assembly process more reliable and easier to control.
Solution Approach 2:
The adhesive members are designed to self-align and self-bond the support members to the semiconductor chip during the assembly process. This self-service capability reduces the need for complex alignment and bonding equipment, simplifying the manufacturing process while ensuring reliable void-free bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the uniformity and stability of semiconductor packages, reducing the occurrence of voids and delamination, thereby improving manufacturing yield and overall package performance.
Implementation Method 1
adhesive members disposed in contact with each of the second surface and the support members
Implementation Method 2
an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure
Data Source
AI summary
A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.