Semiconductor Package Support Structure for Reliable Redistribution Wiring

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in ensuring the reliability and efficiency of electrical connections and structural integrity of semiconductor packages, particularly in wafer-level packaging processes.

Innovation Solution

A manufacturing method involving the use of a debond layer, dielectric layers, seed layers, and redistribution circuit structures, along with supporting structures and conductive terminals, to enhance the electrical connections and structural reliability of semiconductor packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wafer-level packaging is used, then manufacturing simplicity is maintained, but electrical connection reliability and structural integrity deteriorate

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpackaging structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The packaging structure is segmented into multiple functional layers: carrier substrate, debond layer, dielectric layers, seed layers, redistribution circuit structures, supporting structures, and encapsulant. Each layer performs a specific function, allowing the complex requirements for electrical connection reliability to be distributed across multiple specialized components rather than requiring a single complex structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar wafer-level packaging to a three-dimensional stacked architecture. Semiconductor dies are vertically stacked on the carrier substrate with multiple interlayer connections, enabling improved electrical connection reliability through vertical integration and multiple bonding interfaces rather than relying solely on planar connections.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Strength

If conventional wafer-level packaging is used, then manufacturing process simplicity is maintained, but structural integrity deteriorates

Engineering Contradiction:

Improvestructural integrityVSAvoidmanufacturing process complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The supporting structures are formed on the carrier substrate before the semiconductor dies are attached. This preliminary action provides mechanical reinforcement to the carrier substrate in advance, preventing structural failures during subsequent die attachment and packaging processes, thereby improving structural integrity without requiring complex post-assembly reinforcements.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The packaging structure employs composite materials including the debond layer (providing controlled adhesion), dielectric layers (providing electrical isolation and mechanical support), and encapsulant (providing environmental protection and structural consolidation). This composite approach enhances overall structural integrity by combining materials with complementary mechanical properties.

Inventive Principle:

Principle #40Composite materials

3Productivity

If wafer-level packaging is implemented, then productivity is improved, but manufacturing precision deteriorates

Engineering Contradiction:

Improvepackaging throughputVSAvoidelectrical connection precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The redistribution circuit structures serve as intermediary elements between the bond pads on the semiconductor dies and the external connection interfaces. These redistribution layers provide additional alignment tolerance and routing flexibility, enabling precise electrical connections to be achieved even with the variations inherent in high-volume wafer-level packaging processes.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes controlled changes in material properties and process parameters, such as the debond layer's adhesion characteristics and the dielectric layers' thickness and permittivity, to optimize both the precision of electrical connections and the throughput of the packaging process. By adjusting these parameters, the manufacturing process achieves high precision without sacrificing productivity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12476223B2Semiconductor package and method of manufacturing the same

Publication Date: 2025.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.