Semiconductor Package Layout to Cut Switching Loss in Multi-Chip MOSFETs
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Solution Overview
Problem
Existing semiconductor devices face increased resistance and inductance due to bonding wires and stacked wirings, leading to switching loss and challenges in miniaturization and heat dissipation, particularly in multi-chip configurations with power MOS transistors.
Innovation Solution
A semiconductor device design featuring conductive layers and die pads sealed with a resin layer, with passive elements connected to these layers to reduce resistance and inductance, and a manufacturing method that includes etching a metal plate to form die pads and conductive layers, allowing for improved electrical connections and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If surface mounting with bonding wires is used to connect electronic components, then the components can be mounted on a multi-layered board, but the resistance and inductance between components increase and switching loss occurs
Solution Approach 1:
The invention extracts and eliminates the bonding wires that cause high resistance and inductance. By directly mounting the semiconductor chip on the lead frame without bonding wires, the harmful electrical path is removed, thereby reducing switching loss while maintaining manufacturing feasibility through bump connections.
Solution Approach 2:
The invention transitions from planar surface mounting to three-dimensional vertical mounting. The semiconductor chip is mounted vertically on the lead frame with bump connections, creating a shorter electrical path in the vertical dimension rather than relying on horizontal bonding wires, thus reducing resistance and inductance.
2Adaptability or versatility
If surface mounting with multiple components is used, then various electronic components can be integrated, but the mounting area increases and package miniaturization becomes difficult
Solution Approach 1:
The invention merges the semiconductor chip and passive elements into a single integrated module mounted on the lead frame. By combining multiple components and their connections into one compact unit with vertical architecture, the overall package size is reduced while maintaining full component functionality and integration.
Solution Approach 2:
The invention utilizes vertical stacking in the third dimension to arrange components and electrical paths. Instead of spreading components horizontally across a large area, the chip and passive elements are stacked vertically with short interconnections, achieving high integration density in a compact package footprint.
3Ease of manufacture
If flip-chip mounting with lead frame is used, then the semiconductor chip can be connected to terminals, but the electrical path length increases and resistance and inductance increase
Solution Approach 1:
The invention extracts and removes the excessive electrical path length inherent in conventional flip-chip mounting. By optimizing the bump connection positions and creating direct vertical paths from chip pads to lead frame terminals, the unnecessary electrical path segments are eliminated, reducing resistance and inductance despite maintaining manufacturing simplicity.
Data Source
AI summary
Performance of a semiconductor device is improved. A semiconductor device 1 includes a die pad 2a made of a conductive material, a semiconductor chip CHI provided on an upper surface of the die pad 2a, and a semiconductor chip CH3. The semiconductor chip CHI has a gate pad electrode GP1 and a drain pad electrode DP1, and the semiconductor chip CH3 has a pad electrode AP1. A conductive layer 3 is provided on each upper surface of the gate pad electrode GP1 and the pad electrode AP1 so as to be electrically connected to the gate pad electrode GP1 and the pad electrode AP1. The die pad 2a, the semiconductor chip CH1, the semiconductor chip CH3, and the conductive layer 3 are sealed with a resin layer 5 such that an upper surface of the conductive layer 3 and a lower surface of die pad 2a are exposed. A passive element member 7 including one or more passive elements is provided on upper surfaces of the two conductive layers 3.