Semiconductor Package Terminal Area Ratio for Chip Stability

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Solution Overview

Problem

The challenge is to prevent the inclination of stacked semiconductor chips in thinner semiconductor packages and effectively dissipate the heat generated by the chips, as the thickness of semiconductor packages decreases, leading to instability and heat management issues.

Innovation Solution

A semiconductor package design that includes a package substrate with first and second semiconductor chips, where the connection terminals on each chip are strategically arranged to ensure balanced force distribution and uniform bonding, using a combination of signal and dummy connection terminals to maintain chip alignment and facilitate heat dissipation through a molding material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the thickness of the semiconductor package is decreased to meet slimming trends, then more semiconductor chips can be stacked, but the chips become prone to inclination and instability

Engineering Contradiction:
Improvepackage thicknessVSAvoidchip stacking stability
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The connection terminals are segmented into signal connection terminals and dummy connection terminals, with the dummy terminals specifically positioned to provide mechanical support and prevent chip inclination while signal terminals handle electrical connections

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy connection terminals are pre-positioned at specific locations on the package substrate before chip stacking to provide preliminary mechanical support and constraint, preventing chip inclination from the outset

Inventive Principle:
Principle #10Preliminary action

2Volume of moving object

If the thickness of the semiconductor package is decreased, then more chips can be stacked, but heat dissipation becomes more difficult

Engineering Contradiction:
Improvepackage thicknessVSAvoidheat dissipation efficiency
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

Heat dissipation is addressed by extending the thermal management solution to the lateral dimension through strategically positioned dummy connection terminals that serve as thermal pathways, complementing the vertical stacking approach

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Stability of the object's composition

If connection terminals are arranged to ensure uniform bonding, then chip inclination is prevented, but the design complexity increases

Engineering Contradiction:
Improvebonding uniformityVSAvoidterminal arrangement complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The dummy connection terminals serve multiple functions simultaneously: providing mechanical support to prevent chip inclination, facilitating heat dissipation, and maintaining bonding uniformity, thereby reducing overall design complexity despite the added terminal types

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11462479B2Semiconductor package
Publication Date: 2022.10.04 SAMSUNG ELECTRONICS CO LTD
  • US11462479B2 patent drawing
  • US11462479B2 patent drawing
  • US11462479B2 patent drawing

AI summary

A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.