Semiconductor Package Terminal Layout for Crosstalk-Resistant Memory Modules

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Solution Overview

Problem

Existing semiconductor packages face challenges in reducing crosstalk between connection terminals, which affects signal integrity and reliability, particularly in two-dimensional array structures.

Innovation Solution

The semiconductor package employs a two-dimensional array structure for connection terminals, arranging DQ and CA terminals in a diagonal direction and incorporating ground terminals to minimize crosstalk, with a dovetail joint structure between channel regions to enhance signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If connection terminals are arranged in a two-dimensional array structure, then the density and capacity of the semiconductor package are improved, but crosstalk between terminals increases affecting signal integrity

Engineering Contradiction:
Improveterminal densityVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the two-dimensional terminal array into multiple channel regions (first channel region, second channel region, etc.) with alternating orientations. Each channel region contains terminals arranged in a specific direction (first direction or second direction), creating distinct signal pathways that reduce electromagnetic interference and crosstalk between adjacent terminals while maintaining high density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs asymmetric arrangement where adjacent channel regions have different terminal orientation patterns. The first channel region has terminals arranged in the first direction while the second channel region has terminals arranged in the second direction perpendicular to the first. This asymmetric, alternating pattern disrupts the regular grid structure that causes crosstalk, thereby improving signal integrity while preserving terminal density.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If DQ and CA terminals are arranged in diagonal direction, then crosstalk is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecrosstalk reductionVSAvoidterminal arrangement complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent divides the terminal array into discrete channel regions with uniform internal patterns. Within each channel region, terminals are arranged in a simple linear fashion along one direction. The diagonal arrangement emerges from the alternating orientation of adjacent regions rather than complex individual terminal positioning, simplifying the manufacturing process while achieving crosstalk reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines simple linear terminal arrangements within each channel region to create the overall diagonal pattern. By merging multiple simple linear arrays with alternating orientations, the system achieves the crosstalk-reducing diagonal effect without requiring complex manufacturing for each individual terminal position.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If channel regions are coupled in dovetail joint structure, then signal integrity is enhanced, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidchannel region coupling structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dovetail joint structure creates an asymmetric coupling between channel regions, with interlocking features that provide mechanical stability and electrical continuity. This asymmetric design enhances signal integrity by ensuring proper alignment and connection between regions while the modular nature keeps the overall device complexity manageable through standardized interface patterns.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12532756B2Semiconductor package, and memory module including the same
Publication Date: 2026.01.20 SAMSUNG ELECTRONICS CO LTD
  • US12532756B2 patent drawing
  • US12532756B2 patent drawing
  • US12532756B2 patent drawing

AI summary

Provided is a semiconductor package with high reliability signal characteristics and a memory module including the semiconductor package. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, and connection terminals arranged on a lower surface of the package substrate. The connection terminals are arranged in a two-dimensional array structure in a first direction and a second direction perpendicular to the first direction, and two adjacent terminals with a shortest distance therebetween among data signal (DQ) terminals and command and address signal (CA) terminals included in the connection terminals are arranged in a diagonal direction between the first direction and the second direction.