Semiconductor Package Test Pad Structure for Clean Bonding Surfaces

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in maintaining the integrity of test pads during electrical die sorting (EDS) tests, leading to potential contamination and defects in subsequent processes due to non-uniform protrusions formed during the testing process.

Innovation Solution

The semiconductor package design includes a test pad structure with a protrusion that is planarized to form a flat surface higher than the surrounding insulating layer, and a bonding layer covers the protrusion to prevent exposure during planarization, thereby maintaining a clean bonding surface and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a test pad structure with a protrusion is formed during EDS testing, then electrical testing can be performed, but the protrusion causes non-uniform surfaces leading to contamination and defects in subsequent processes

Engineering Contradiction:
ImproveEDS testing capabilityVSAvoidsurface uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarization layer before subsequent bonding processes to pre-address the surface uniformity issue. The protrusion is intentionally designed with the understanding that it will be planarized in advance, allowing the EDS test to proceed while ensuring the surface will be uniform for bonding. This resolves the contradiction by preparing the solution in advance rather than trying to eliminate the protrusion entirely.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful protrusion into a beneficial feature by designing the test pad structure to include a protrusion that can be easily identified and planarized. The protrusion serves as a marker for where planarization should occur, and its presence ensures that the planarization process is applied correctly. This transforms the potential defect into a useful guide for manufacturing.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Device complexity

If the test pad protrusion is left exposed, then the test pad structure remains simple, but contamination occurs during subsequent bonding processes

Engineering Contradiction:
Improvetest pad structureVSAvoidbonding quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary element - the planarization layer - that sits between the protruding test pad and the subsequent bonding process. This intermediate layer serves multiple functions: it covers the protrusion to prevent contamination, provides a uniform surface for bonding, and can be removed or integrated in subsequent steps. This intermediary resolves the contradiction by adding a controlled element that protects against harmful effects while maintaining the beneficial test pad structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If planarization is performed to remove the protrusion, then surface uniformity is improved, but the test pad may become exposed or contaminated during the process

Engineering Contradiction:
Improvesurface flatnessVSAvoidcontamination risk
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by designing the test pad protrusion to extend above the insulating layer surface, creating a built-in protective feature before the planarization process. This protrusion acts as a cushion or buffer that can be selectively removed or planarized without affecting the underlying test pad structure. The design ensures that even if planarization varies, the test pad remains protected and uncontaminated.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12500189B2Semiconductor package
Publication Date: 2025.12.16 SAMSUNG ELECTRONICS CO LTD
  • US12500189B2 patent drawing
  • US12500189B2 patent drawing
  • US12500189B2 patent drawing

AI summary

A semiconductor package includes a first structure having a first insulating layer and a first bonding pad penetrating the first insulating layer, and a second structure on the first structure and having a second insulating layer bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the first bonding pad, and a test pad structure penetrating the second insulating layer and including a test pad in an opening penetrating the second insulating layer and having a protrusion with a flat surface, and a bonding layer filling the opening and covering the test pad and the flat surface, the protrusion of the test pad extending from a surface in contact with the bonding layer, and the flat surface of the protrusion being within the opening and spaced apart from an interface between the bonding layer and the first insulating layer.