Multi-Chip Semiconductor Package Testing via Chip Enable Reduction

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Solution Overview

Problem

The complexity of testing semiconductor packages with multiple chips leads to measurement errors due to leakage currents from inactivated chips, which complicates the testing process and reduces the reliability of semiconductor package testing.

Innovation Solution

A method and device for testing semiconductor packages that simultaneously sense electrical signals from multiple activated semiconductor chip groups, using a Chip Enable Reduction (CER) command to activate at least two chips and sum their outputs, allowing for accurate determination of package defects by comparing the sensed signals with a reference table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Weight of moving object

If multiple semiconductor chips are mounted in one package to reduce the number of mounted parts, then the electronic device becomes smaller and lighter, but the test complexity increases and measurement errors occur due to leakage currents from inactivated chips

Engineering Contradiction:

Improveweight of electronic deviceVSAvoidmeasurement precision of electrical signals

Core Design Contradiction:

Weight of moving objectVSMeasurement precision

Solution Approach 1:

The patent divides the testing process into multiple steps where chips are activated and tested individually. By segmenting the testing of multiple chips into separate activation phases, the system can isolate and measure electrical signals from specific chips without interference from leakage currents of inactivated chips, thus maintaining measurement precision while testing integrated multi-chip packages.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary activation of specific chip groups before measurement. By preliminarily controlling which chips are activated through the control circuit, the system prepares the test conditions in advance, ensuring that only the intended chips are in active state during measurement, thereby preventing leakage current interference and improving measurement accuracy.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If equipment for testing the semiconductor package is enlarged to handle complex testing requirements, then the testing capability improves, but the device complexity increases

Engineering Contradiction:

Improvetesting capability for multi-chip packageVSAvoidcomplexity of testing equipment

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal testing approach where a single test device can accommodate multiple semiconductor chips through the control circuit's ability to selectively activate different chip groups. The control circuit serves multiple functions: it manages chip activation, controls signal routing, and coordinates measurement sequences, thereby providing versatile testing capability without requiring separate specialized equipment for each chip.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control circuit acts as an intermediary between the test device and the semiconductor chips. It mediates the interaction by receiving test commands, determining which chips to activate, controlling signal distribution, and managing the measurement process. This intermediary function simplifies the overall system architecture compared to having direct complex connections between the test device and each chip individually.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If leakage currents from inactivated chips are not accounted for, then the testing process is simpler, but measurement errors increase and test reliability decreases

Engineering Contradiction:

Improvetesting efficiencyVSAvoidreliability of test results

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent incorporates feedback mechanisms where the control circuit continuously monitors the electrical signals from activated chip groups and compares them against expected values. By providing feedback on the measured signals, the system can detect and compensate for leakage current effects, ensuring accurate measurement results while maintaining efficient testing through automated real-time monitoring and adjustment.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11568949B2Semiconductor package test method, semiconductor package test device and semiconductor package

Publication Date: 2023.01.31 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.