Bottom-Side Semiconductor Package with Integrated Thermal Terminal

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Solution Overview

Problem

Existing semiconductor packages lack an integrated heatsink and electrical connection feature, relying on additional parts for heat dissipation and requiring assembly of a 3D clip structure.

Innovation Solution

A method of manufacturing a semiconductor package with conductive terminals on the bottom side, where the semiconductor die is attached to the terminals using lead-free adhesives, and a conductive layer is plated to establish electrical connections, with an encapsulant opening for exposed terminals and a singulating process to separate the package from the lead frame.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a 3D clip structure is used for heat dissipation, then heat dissipation capability is improved, but device complexity and assembly requirements increase

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidassembly complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent combines the heatsink function and electrical connection function into a single integrated bottom-side terminal structure. The conductive terminals on the bottom side serve dual purposes: providing electrical connectivity and acting as heatsinks for thermal management, thereby eliminating the need for separate 3D clip structures and reducing assembly complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bottom-side conductive terminals are designed to perform multiple functions simultaneously: electrical connection, heat dissipation, and mechanical support. This multi-functionality replaces the need for dedicated heatsink components and simplifies the overall device architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Temperature

If additional parts are used for heat dissipation, then heat dissipation capability is improved, but device complexity increases

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidnumber of parts
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent merges the heatsink function with the existing electrical connection terminals. The bottom-side terminals are designed to conduct heat away from the semiconductor die while simultaneously providing electrical connectivity, thereby eliminating the need for additional heatsink parts

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive terminals are designed as multi-functional elements that serve both electrical and thermal management purposes. This universality reduces the total part count by eliminating dedicated thermal management components

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Strength

If lead-based adhesives are used for attaching semiconductor die, then bonding strength is improved, but compliance with RoHS regulations deteriorates

Engineering Contradiction:
Improvebonding strengthVSAvoidRoHS compliance
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The patent changes the material composition parameter of the adhesive from lead-based to lead-free formulations (such as eutectic bonding, Ag-containing adhesives, or Ag sintering material). This parameter change maintains bonding functionality while achieving RoHS compliance by eliminating hazardous lead content

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides an integrated heatsink and electrical connection feature, enhancing heat dissipation and compliance with RoHS regulations while maintaining effective electrical connectivity.

Implementation Method 1

partially plating a conductive layer on the bottom side, electrically connecting the semiconductor die via the at least one opening with the portion of at least one terminal exposed from the encapsulant

Methodology Applied
Scientific EffectPlating: Electroplating

Implementation Method 2

the semiconductor die is attached to the terminal using eutectic bonding preferably CuSn eutectic, Ag containing adhesives or Ag sintering material

Methodology Applied
Scientific EffectEutectic bonding: Soldering

Data Source

PatentEP4350765A1A method of manufacturing a semiconductor package, such semiconductor package as well as an electronic system comprising a PCB element and at least such semiconductor package
Publication Date: 2024.04.10 NEXPERIA BV
  • EP4350765A1 patent drawingFigure 1
  • EP4350765A1 patent drawingFigure 2
  • EP4350765A1 patent drawingFigure 3

AI summary

Proposed is a method of manufacturing a semiconductor package having at least one semiconductor die connected with at least one conductive terminal, wherein the semiconductor package has an upper side and a bottom side and wherein the at least one terminal is located at least partially on the bottom side, the method comprising the steps of: a) providing a lead frame having a plurality of terminals for establishing external electrical connections; b) providing the at least one semiconductor die and electrically and mechanically attaching the at least one semiconductor die to the at least one terminal of the lead frame located at least partially on the bottom side; c) providing an encapsulant over the semiconductor die and the plurality of terminals leaving at least a portion of at least one terminal exposed wherein on the bottom side the encapsulant is provided with at least one opening (8) that at least partially is exposing the semiconductor die; and d) cleaning the bottom side of the semiconductor package; e) partially plating a conductive layer on the bottom side, electrically connecting the semiconductor die via the at least one opening with the portion of at least one terminal exposed from the encapsulant; and f) singulating the semiconductor package from the lead frame.