Semiconductor Package Thermal Via and Rear Surface Pads

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving high integration and high-speed performance while effectively managing heat dissipation and signal transmission in stacked chip configurations.

Innovation Solution

The semiconductor package design includes stacked semiconductor chips with a lower chip featuring via electrodes and signal/thermal pads, and an upper chip with a wiring structure and vias connected by signal and thermal bumps, allowing for efficient heat dissipation and signal transmission between chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor chips are stacked vertically to achieve high integration, then the integration density is improved, but heat dissipation becomes more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidheat dissipation
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent introduces dedicated thermal via holes extending through the substrate thickness direction (vertical dimension) and thermal pads on the rear surface, creating a three-dimensional heat dissipation pathway. This moves heat management from a two-dimensional surface problem to a three-dimensional volumetric solution, allowing heat to be conducted vertically through the substrate and dissipated at the rear surface, thereby resolving the heat dissipation difficulty in vertically stacked high-integration packages.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If more via electrodes and wiring structures are added to increase signal transmission capacity, then the signal transmission capability is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improvesignal transmission capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The substrate serves multiple functions simultaneously: it provides mechanical support, contains signal transmission pathways (via holes and wiring layers), and acts as a thermal management system (thermal via holes and thermal pads). By integrating signal and thermal management functions into a single multi-functional substrate structure, the patent reduces the need for separate components and assembly steps, thereby decreasing manufacturing complexity while maintaining high signal transmission capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the reliability and operational stability of semiconductor packages by enabling effective heat transfer and signal connectivity between stacked chips, addressing the limitations of existing technologies.

Implementation Method 1

entire bottom surfaces of the plurality of rear surface thermal pads may in contact with the rear surface protecting layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a plurality of thermal bumps connecting between the plurality of rear surface thermal pads and the plurality of thermal vias

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11721604B2Semiconductor package
Publication Date: 2023.08.08 SAMSUNG ELECTRONICS CO LTD
  • US11721604B2 patent drawing
  • US11721604B2 patent drawing
  • US11721604B2 patent drawing

AI summary

Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.