3D Semiconductor Package Structure for Crack-Resistant Thin Dies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Thinned semiconductor dies in 3D stacked package structures are prone to cracking during the pick process and may experience warpage due to thermal expansion and contraction, leading to yield losses.
Innovation Solution
A semiconductor package structure featuring first and second semiconductor dies with pillar structures and an encapsulant, where the second die is electrically connected to the first die, and the encapsulant covers both, with the lower surface of the encapsulant being coplanar with the pillar structures and the second die, allowing for reduced thickness and minimizing cracking and warpage through a manufacturing method involving pillar structures and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the semiconductor die is thinned to reduce package thickness, then the overall package thickness is reduced, but the die becomes prone to cracking during pick process and warpage during bonding
Solution Approach 1:
The patent divides the semiconductor die into multiple thinner layers (first semiconductor die layer, second semiconductor die layer, etc.) separated by interlayer insulating films. This segmentation allows each layer to be thinner and more flexible, reducing the risk of cracking during pick process while maintaining overall structural integrity. The multiple layers can independently accommodate thermal expansion without causing warpage.
Solution Approach 2:
The patent uses composite material structure consisting of alternating semiconductor die layers and interlayer insulating films. This composite structure provides mechanical support and stress distribution, preventing cracking in the thinned semiconductor layers while the different materials' thermal expansion properties reduce warpage during bonding processes.
2Length of stationary object
If the semiconductor die is thinned to reduce package thickness, then the overall package thickness is reduced, but manufacturing yield decreases due to cracking and warpage
Solution Approach 1:
By segmenting the die into multiple thin layers with insulating films, the structure becomes more robust against manufacturing defects. Each layer can be processed and handled independently, reducing the cumulative risk of cracking and improving overall manufacturing yield despite reduced individual layer thickness.
Solution Approach 2:
The interlayer insulating films act as cushioning layers between the thinned semiconductor die layers. These films provide mechanical protection and stress relief before cracking can propagate, thereby preventing yield losses during pick and bonding processes while maintaining the thinned profile.
3Reliability
If pillar structures are added for vertical electrical connection, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the pillar structure formation with the existing semiconductor die layer stacking process. The pillars are integrated within the multi-layer structure, sharing the same fabrication steps for layer deposition and patterning, thereby reducing overall process complexity while achieving vertical electrical connection.
Solution Approach 2:
The interlayer insulating films serve multiple functions: they provide electrical insulation between semiconductor layers, act as mechanical support to prevent cracking, and serve as a base for pillar structure formation. This multi-functionality reduces the need for additional dedicated structures, simplifying the overall device complexity.
Data Source
AI summary
A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.