Semiconductor Package Layout With Exposed Interconnects and Thin Stacking
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Solution Overview
Problem
Semiconductor device packages face challenges in balancing area and thickness, as arranging electronic components side-by-side increases area while stacking increases thickness, hindering connection to other substrates like circuit boards.
Innovation Solution
A semiconductor device package design featuring a substrate with a connection structure and a package body that covers electronic components, exposing a portion for electrical connection, allowing for efficient electrical connectivity while minimizing thickness through strategic packaging and shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If electronic components are arranged side-by-side on the substrate, then the functionality and performance of the semiconductor device package is increased, but the area of the semiconductor device package increases
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side arrangement to a three-dimensional configuration by stacking electronic components vertically on the substrate. This allows multiple components to be positioned at different heights (Z-axis) while occupying the same horizontal footprint, thereby increasing functionality without proportionally increasing the package area.
Solution Approach 2:
The patent implements a nested structure where electronic components are stacked vertically, with each component positioned on top of the previous one. This nesting approach allows multiple components to occupy overlapping horizontal spaces at different vertical levels, maximizing space utilization and reducing the overall package area while maintaining multiple functionalities.
2Area of stationary object
If electronic components are arranged in a stacking arrangement, then the area of the semiconductor device package is reduced, but the thickness of the semiconductor device package increases
Solution Approach 1:
The patent employs a thin package body structure that encapsulates the stacked electronic components. This thin film approach allows the package to maintain a compact vertical profile while accommodating multiple stacked components, thereby reducing the overall thickness increase that would otherwise result from the stacking arrangement.
Solution Approach 2:
The patent optimizes the vertical stacking configuration to minimize the Z-axis height by carefully selecting component orientations and interconnection methods. This dimensional optimization allows the benefits of stacking (reduced area) to be achieved while controlling the thickness increase through efficient use of vertical space.
3Reliability
If the connection structure is covered by the package body, then the electronic components are protected, but electrical connection to other substrates becomes difficult
Solution Approach 1:
The patent extracts the connection structure from full encapsulation by providing openings or windows in the package body at strategic locations. This allows the connection structures to remain partially exposed or accessible through the package body, enabling electrical connection to other substrates while the majority of the electronic components remain protected by the package body.
Solution Approach 2:
The patent introduces connection structures as intermediary elements that extend from the stacked electronic components through the package body to the external environment. These connection structures serve as mediators that maintain electrical connectivity to other substrates while allowing the package body to provide protection to the internal electronic components.
Data Source
AI summary
A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.