Semiconductor Package With Through Electrode Opening
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Solution Overview
Problem
Conventional semiconductor package manufacturing requires high-cost wafer supporting systems and can damage through electrodes during planarization processes, leading to increased costs and reduced yield rates due to the need for thin wafer handling and exposure of electrodes.
Innovation Solution
A semiconductor package design featuring a substrate with through electrodes extending from one surface and an opening formed to expose these electrodes, allowing for the mounting of additional chips and a sealing member within the opening, which reduces the need for high-cost wafer handling systems and minimizes damage to electrodes by maintaining a thicker peripheral substrate and using a localized wet etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the backside of the substrate is planarized to expose the through electrode, then the thickness of the substrate is decreased and the through electrode is exposed, but a high-cost wafer supporting system is required and the through electrodes may be damaged
Solution Approach 1:
The substrate is segmented into two regions: a first region where the backside is planarized to expose through electrodes for electrical connection, and a second region where the backside is not planarized to maintain sufficient thickness for mechanical support. This segmentation allows the package to achieve both electrode exposure and structural stability without requiring expensive wafer supporting systems throughout the entire substrate area.
2Manufacturing precision
If the backside of the substrate is planarized to expose the through electrode, then the through electrode is exposed for connection, but the through electrodes may be damaged by the planarization process
Solution Approach 1:
The substrate is segmented into a first region where planarization exposes through electrodes and a second region where planarization is avoided to preserve electrode integrity. By limiting the planarization process to only the necessary area, the through electrodes are exposed for connection without being subjected to damaging mechanical stress from excessive planarization.
3Manufacturing precision
If the substrate is thinned to expose through electrodes, then electrode connection is enabled, but wafer warpage occurs requiring expensive supporting systems
Solution Approach 1:
The substrate is divided into a first region with thinned thickness for electrode exposure and a second region with maintained thickness for structural support. This segmentation enables local thinning to achieve electrode connection while preserving overall wafer flatness and preventing warpage without requiring expensive supporting systems across the entire substrate.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.