3D Stacked Semiconductor Package With Vertical Through Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of MOS-FETs in semiconductor devices leads to deterioration in operational properties, necessitating increased integration density and high-performance semiconductor packages.
Innovation Solution
A semiconductor package design featuring a package substrate with upper and lower semiconductor chips, where the lower chip includes power and signal through electrodes penetrating the substrate to enhance electrical connectivity and increase integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then the number of transistors per unit area increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to 3D vertically stacked configurations. Multiple semiconductor chips are stacked in the vertical direction with through electrodes penetrating the substrate, enabling power and signal distribution across three dimensions. This dimensional change allows high integration density while maintaining operational performance through optimized vertical interconnects and separated power/signal regions.
2Quantity of substance
If through electrodes are placed closer together to increase density, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements different through electrode configurations in different regions of the substrate. The power wire region contains first through electrodes with specific spacing optimized for power distribution, while the signal wire region contains second through electrodes with different spacing for signal routing. This local differentiation allows each region to be optimized independently, achieving high overall density while maintaining manufacturable precision requirements for each specific zone.
3Quantity of substance
If power wire region vertically overlaps core region to increase density, then integration density increases, but electrical connectivity complexity increases
Solution Approach 1:
The patent segments the substrate into distinct functional regions: a power wire region containing first through electrodes for power distribution, and a signal wire region containing second through electrodes for signal routing. The core region is positioned to vertically overlap the power wire region, creating a layered functional architecture. This segmentation allows independent optimization of power and signal paths, reducing electrical connectivity complexity despite high vertical integration.
Data Source
AI summary
A semiconductor package is disclosed. The semiconductor package may include a package substrate, an upper semiconductor chip on the package substrate, and a lower semiconductor chip between the package substrate and the upper semiconductor chip. The upper semiconductor chip may include a core region having a power circuit thereon and a logic cell region having a logic circuit thereon. The lower semiconductor chip may include a power wire region vertically overlapping the core region. The lower semiconductor chip may include a first substrate, a first through electrode, and a second through electrode, the first substrate including an active surface having an integrated circuit thereon, and a first through electrode and a second through electrode penetrating the first substrate in the power wire region. A distance between the first and second through electrodes may be smaller than a width of the first through electrode.