Semiconductor Package With Through-Hole Antenna Embedding
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Solution Overview
Problem
The challenge lies in miniaturizing semiconductor packages with double-sided connection circuits for semiconductor chips, as existing technologies face difficulties in reducing size due to spatial limitations and electrical losses from extended signal paths, especially for components like power IC chips that require complex electrical connections.
Innovation Solution
A semiconductor package structure featuring a core structure with opposing surfaces, double-sided wiring layers, through-holes, and redistribution layers to connect contacts on both surfaces of the chip, allowing for efficient connection and miniaturization by embedding chip components within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If components are connected to the surface of a mainboard using conventional mounting methods, then electrical connections can be established, but the module size cannot be miniaturized and electrical losses occur due to extended signal paths
Solution Approach 1:
The patent utilizes the thickness dimension of the semiconductor chip to route connection circuits through the chip body rather than along the surface. By forming connection circuits that extend from the first surface through the thickness to the second surface, the signal path length is dramatically reduced, enabling miniaturization without increasing electrical loss.
Solution Approach 2:
The patent embeds the semiconductor chip within a package structure where connection circuits are nested within the chip thickness. The first and second wiring layers are positioned at opposite surfaces while connection circuits traverse the internal volume, creating a nested configuration that reduces the overall module footprint while maintaining efficient electrical pathways.
2Reliability
If double-sided connection circuits are implemented for power IC chips, then electrical connections can be established on both surfaces, but the package structure becomes complicated and difficult to miniaturize
Solution Approach 1:
The patent merges the first and second wiring layers into a single integrated package structure. The connection circuits are formed to traverse the chip thickness and connect both surfaces, combining what would otherwise be separate connection systems into a unified double-sided connection architecture that reduces overall complexity.
Solution Approach 2:
The patent segments the connection path into distinct portions: first wiring layer at the first surface, connection circuits traversing the chip thickness, and second wiring layer at the second surface. This segmentation allows each component to be optimized independently while maintaining a relatively simple overall package structure.
3Reliability
If signal paths are extended to connect components on the mainboard surface, then electrical connections can be established, but electrical losses increase
Solution Approach 1:
The patent transitions the connection path from a two-dimensional surface route to a three-dimensional path through the chip thickness. By utilizing the vertical dimension, the connection circuits achieve shorter path lengths compared to surface-mounted connections, thereby reducing electrical loss while maintaining reliable electrical connection.
Data Source
AI summary
A semiconductor package includes: a core structure having first and second surfaces and having first and second through-holes; a first semiconductor chip embedded in the core structure and having first and second contacts disposed on two opposing surfaces thereof, respectively; a first wiring layer on the surface of the core structure and connected to the first contact; a second wiring layer on the second surface of the core structure and connected to the second contact; a chip antenna disposed in the first through-hole; a second semiconductor chip in the second through-hole and having a connection pad; a first redistribution layer on the first surface of the core structure and connected to the connection terminal, the connection pad, and the first wiring layer; an encapsulant encapsulating the chip antenna and the second semiconductor chip; and a second redistribution layer on the encapsulant connecting to the second wiring layer.