Semiconductor Package With Through-Hole Passive Components

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Solution Overview

Problem

Conventional semiconductor packaging technologies require large mounting areas due to minimum component intervals, leading to high electromagnetic interference and increased electrical noise, and face challenges with process defects like undulations and cracks, especially when integrating semiconductor chips with passive components.

Innovation Solution

A novel semiconductor package structure that modularizes passive components and semiconductor chips in a single package, using a core member with through-holes of varying depths to reduce mounting area and electrical path length, and employs a laser-via hole process for efficient connection of passive component electrodes to connection vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional chip-on-board technology is used to mount passive components and semiconductor packages on a printed circuit board, then cost effectiveness is improved, but mounting area increases and electromagnetic interference between components increases

Engineering Contradiction:

Improvecost effectivenessVSAvoidmounting area

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the semiconductor chip and passive components into a single integrated package structure. The passive components are mounted on a carrier substrate, and the semiconductor chip is mounted on top of the carrier substrate, creating a compact module that reduces the overall mounting area on the printed circuit board while maintaining cost effectiveness through integrated manufacturing processes

Inventive Principle:

Principle #5Merging (Combining)

2Ease of manufacture

If conventional chip-on-board technology is used to mount passive components and semiconductor packages on a printed circuit board, then cost effectiveness is improved, but electromagnetic interference between components increases

Engineering Contradiction:

Improvecost effectivenessVSAvoidelectromagnetic interference

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If the semiconductor chip and passive components are mounted separately on a printed circuit board, then manufacturing simplicity is improved, but the distance between components increases leading to increased electrical noise

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidelectrical noise

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a nested structure where the semiconductor chip is mounted on top of the carrier substrate that already holds the passive components. This vertical stacking arrangement places components in three-dimensional space, significantly reducing the horizontal distance between them and minimizing electrical noise while maintaining manufacturing simplicity

Inventive Principle:

Principle #7Nested doll (Nesting)

4Ease of manufacture

If through-holes of equal depth are used for both semiconductor chip and passive component mounting, then manufacturing simplicity is improved, but process defects such as undulations and cracks increase

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidprocess defects

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating through-holes of different depths tailored to the specific requirements of each component type. Passive components are mounted in first through-holes with a first depth, while the semiconductor chip is mounted in a second through-hole with a second depth greater than the first depth. This localized differentiation in hole depth allows each component to be properly positioned and secured, reducing process defects such as undulations and cracks while maintaining manufacturing simplicity through a unified carrier substrate approach

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10727212B2Semiconductor package

Publication Date: 2020.07.28 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.