Semiconductor Package Through Hole Placement for Thermal Stress
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Solution Overview
Problem
Semiconductor packages with stacked chip technology face reliability issues due to thermal expansion coefficient differences between the package substrate and semiconductor chips, leading to signal pattern cracking and deterioration.
Innovation Solution
Incorporating through holes in the intermediate layer of the package substrate, positioned outside the separation region, to connect signal patterns with chip ball lands, thereby avoiding the separation region and minimizing the impact of thermal expansion coefficient differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through holes are positioned in the separation region to connect signal patterns with chip ball lands, then electrical connection is achieved, but thermal expansion coefficient differences cause signal pattern cracking and reliability deterioration
Solution Approach 1:
The patent extracts the harmful separation region from the path of signal patterns by positioning through holes exclusively in chip regions. This removes the vulnerable interface between different materials (substrate and chip) from the stress path, eliminating the source of thermal expansion cracking while maintaining electrical connectivity.
Solution Approach 2:
The patent applies local quality by creating region-specific through hole placement: chip regions contain through holes for signal patterns, while separation regions exclude them. This localized differentiation allows signal patterns to traverse only through homogeneous material (substrate in chip regions), avoiding the heterogeneous interface in separation regions that causes thermal stress concentration.
2Quantity of substance
If stack package technology is used to increase capacity, then density and weight are improved, but thermal expansion coefficient differences lead to cracking and reliability issues
Solution Approach 1:
The patent segments the substrate into distinct chip regions and separation regions, with through holes confined to chip regions only. This segmentation allows the package to maintain high capacity through vertical stacking while isolating signal paths from thermal stress zones, thereby preserving reliability in multi-chip configurations.
Data Source
AI summary
A semiconductor package, comprising: a package substrate including chip regions, a separation region between the chip regions, and an edge region around the chip and separation regions; semiconductor chips disposed on the chip regions of the package substrate; and signal patterns. The package substrate comprises an upper layer substantially adjacent to the semiconductor chips, a lower layer including interconnection structures disposed in the chip regions, and an intermediate layer between the upper and lower layers, the intermediate layer includes through holes disposed only outside of the separation region; and the signal patterns are in contact with the interconnection structures through the through holes.