Semiconductor Package With Through-Hole Wiring Board

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Solution Overview

Problem

Current semiconductor packaging techniques face challenges in increasing memory capacity while maintaining a small size, requiring advanced methods to integrate multiple cells in a limited space and achieve high performance, especially in achieving a high degree of freedom in solder ball layout for flip chip bonding.

Innovation Solution

A semiconductor package design featuring a wiring board with a through-hole and a molding region, where a semiconductor chip is mounted using flip chip bonding, and a sacrificial layer is used to facilitate the molding process, allowing for increased freedom in solder ball layout and preventing voids between the chip and the board.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a semiconductor chip is mounted using flip chip bonding method with conventional packaging, then the chip can be electrically connected to the wiring board, but the solder ball layout freedom is limited and voids may form during molding

Engineering Contradiction:
Improvesolder ball layout freedomVSAvoidvoid prevention
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces through-holes that divide the mounting region into separate zones, allowing independent placement of solder balls in different areas. This segmentation enables flexible solder ball layouts while the molding material flows through the holes to prevent void formation during packaging.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The through-holes act as intermediary structures that facilitate both solder ball placement flexibility and void prevention. These holes allow molding material to penetrate and fill potential void spaces, serving as a mediator between the conflicting requirements of layout freedom and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If multiple semiconductor chips are integrated in a limited space to increase memory capacity, then the package size remains small, but the manufacturing complexity increases

Engineering Contradiction:
Improvememory capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The through-hole structure serves multiple functions simultaneously: it enables flexible solder ball layouts for different chip configurations, facilitates molding material flow to prevent voids, and supports the integration of multiple chips in various arrangements. This multi-functionality reduces manufacturing complexity despite high integration requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes vertical through-holes to create three-dimensional space utilization, allowing solder balls and molding material to occupy vertical space rather than only horizontal plane. This dimensional approach enables higher integration density without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Strength

If the molding region is surrounded by a wiring board structure, then the package provides structural support, but the through-hole filling requirement increases manufacturing steps

Engineering Contradiction:
Improvestructural supportVSAvoidmolding process simplicity
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The through-holes are formed in the wiring board before chip mounting and molding processes. This preliminary action prepares the structure for subsequent flexible solder ball placement and simplifies the molding process by pre-establishing pathways for material flow, reducing the need for additional manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9196538B2Semiconductor package and method of fabricating the same
Publication Date: 2015.11.24 SAMSUNG ELECTRONICS CO LTD
  • US9196538B2 patent drawing
  • US9196538B2 patent drawing
  • US9196538B2 patent drawing

AI summary

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.