Semiconductor Package With Through Openings for Void-Free Underfill
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Solution Overview
Problem
The existing semiconductor package manufacturing process faces challenges with slow underfill flow leading to voids between stacked semiconductor chips and potential damage due to pressure from the epoxy molding compound (EMC), particularly at the central portion of the chip where stress is concentrated.
Innovation Solution
The semiconductor package design includes a substrate with through openings that allow the molding material to flow efficiently between and within the semiconductor chips, reducing void formation and chip damage by enabling the material to fill spaces through multiple pathways, including through openings in the substrate and chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the underfill process is used to fill spaces between stacked semiconductor chips, then the chips are protected and bonded, but the flow of underfill solution from the outside toward the center is slow causing void formation between bumps
Solution Approach 1:
The patent introduces through-openings that segment the filling process into multiple pathways: external filling from chip edges and internal filling through the through-openings. This segmentation allows the underfill solution to reach the center of the chip more efficiently through multiple routes simultaneously, preventing void formation while maintaining bonding quality
Solution Approach 2:
The through-openings act as intermediaries that facilitate the flow of underfill solution from the external environment to the internal regions between bumps. These openings serve as mediating channels that enable complete filling without direct reliance on slow external-only flow paths
2Reliability
If the EMC molding process is used to encapsulate semiconductor chips, then the chips are protected, but the pressure from the EMC positioned on the chip causes damage and generates voids between bumps
Solution Approach 1:
The through-openings segment the pressure distribution by providing internal relief pathways. When EMC is applied, the pressure can be released through these openings, preventing concentration of stress at the chip center and reducing the risk of bump damage and void formation while maintaining protective encapsulation
Solution Approach 2:
The through-openings are pre-formed in the chip structure before molding, providing built-in pressure relief pathways that cushion against the harmful effects of EMC pressure. This beforehand preparation prevents pressure-induced damage before it occurs during the molding process
Data Source
AI summary
A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.