Semiconductor Package With Through-Panel Vias For Vertical Stacking
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Solution Overview
Problem
Conventional semiconductor packaging technologies, such as wire bonding, face limitations in stacking multiple layers due to thickness constraints and topology issues, making it difficult to achieve high integration and miniaturization in electronic products.
Innovation Solution
A semiconductor package design utilizing a fan-out packaging technique with through-panel vias (TPVs) and redistribution layers, allowing for vertical stacking of semiconductor chips without wire bonding, enabling increased integration and miniaturization by interconnecting chips through TPVs and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding process is used to electrically connect stacked semiconductor chips, then electrical connection between chips is achieved, but the overall package thickness increases and stacking more than 4 layers becomes difficult
Solution Approach 1:
The patent transitions from horizontal wire bonding to vertical through-panel via connections. By routing electrical connections through the thickness direction of the panel rather than using lateral wires, the package achieves higher integration density without increasing overall thickness, enabling stacking of more than 4 layers.
Solution Approach 2:
The patent extracts and eliminates the wire bonding process from the stacked chip interconnection method. By removing the wire bonding step and replacing it with direct through-panel via connections, the package thickness is reduced while maintaining reliable electrical connectivity between stacked chips.
2Adaptability or versatility
If redistribution layer is used for more than 2 loads, then electrical connection flexibility is improved, but T-topology appears and complicates the structure
Solution Approach 1:
The patent segments the electrical connection paths by providing separate through-panel via routes for each load. Instead of using a complex T-topology redistribution layer, each load has its own dedicated vertical connection path through the panel, simplifying the overall structure while maintaining connection flexibility.
Solution Approach 2:
The patent resolves the T-topology issue by moving connection routing from the horizontal plane to the vertical dimension. Through-panel vias provide direct vertical access to multiple loads, eliminating the need for complex in-plane redistribution layer routing and avoiding T-topology formation.
3Productivity
If fan-out packaging technique is applied with through-panel vias, then integration is increased and miniaturization is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming through-panel vias and accommodating portions in the panel before chip stacking. This advance preparation enables subsequent chip placement and wiring operations to proceed more efficiently, reducing overall manufacturing complexity despite the advanced packaging technique.
Solution Approach 2:
The through-panel vias serve multiple functions: they provide electrical connections, structural support, and alignment references for stacked chips. This multi-functionality reduces the need for additional separate components or processes, offsetting the increased complexity of the fan-out packaging technique.
Data Source
AI summary
A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.