Semiconductor Package With Through Via Chips
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Solution Overview
Problem
The increasing complexity of semiconductor devices with higher I/O terminal density poses challenges in packaging, leading to reduced yield due to the difficulty in integrating more functions into smaller areas.
Innovation Solution
A semiconductor package structure is developed using a method that includes forming a redistribution layer, disposing chips with through via structures for high-density interconnection, and using encapsulants to surround and connect the chips, allowing for fine-pitch interconnects and increased I/O counts without forming through via structures in all chips, thereby improving yield and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through via structures are formed in all chips to achieve high-density interconnection, then I/O counts and integration density increase, but manufacturing complexity and difficulty increase leading to reduced yield
Solution Approach 1:
The patent segments the through via structure formation to only specific chips (second chip) that require high-density interconnection, rather than forming through vias in all chips. This selective approach divides the packaging structure into different functional zones: chips with through vias for high-density areas and chips without through vias for standard areas, thereby reducing overall manufacturing complexity while maintaining high I/O counts where needed
Solution Approach 2:
The patent applies local quality by providing different interconnection structures to different chips based on their specific requirements. The second chip includes through via structures for high-density interconnection areas, while other chips use conventional bonding methods. This localized approach optimizes I/O density in critical areas without unnecessarily complicating the entire packaging process
2Quantity of substance
If more functions are integrated into smaller areas to increase circuit density, then integration density increases, but packaging difficulty increases leading to reduced yield
Solution Approach 1:
The patent transitions from planar integration to three-dimensional integration by stacking multiple chips vertically and using through via structures to establish interconnections between different layers. This vertical dimension allows higher integration density without proportionally increasing the footprint area, while the modular stacked architecture maintains manufacturing ease through standardized assembly processes
3Quantity of substance
If fine-pitch interconnects are implemented to increase I/O terminal density, then I/O terminal density increases, but manufacturing precision requirements increase leading to reduced yield
Solution Approach 1:
The patent introduces an intermediary carrier substrate that holds multiple chips in a stacked configuration during assembly. This carrier acts as a reference plane and positioning fixture, enabling precise alignment of fine-pitch interconnects between chips without requiring extremely tight tolerances in the chip manufacturing itself. The carrier substrate absorbs and compensates for dimensional variations, facilitating high I/O terminal density with manageable precision requirements
Data Source
AI summary
A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.