Semiconductor Package Through-Via Electrode Pad Design

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Solution Overview

Problem

The miniaturization of semiconductor chips and packages has led to handling difficulties, reduced manufacturing yield, and increased production time, affecting productivity and reliability.

Innovation Solution

A semiconductor device design featuring a substrate with a through-via electrode, a spacer insulating layer, and specific silicon oxide and nitride layers to improve handling and manufacturing efficiency, including a method of forming these layers using chemical mechanical polishing to reduce the aspect ratio of the through-via electrode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the size of semiconductor chips and packages is reduced, then miniaturization is achieved, but handling difficulty increases and manufacturing yield decreases

Engineering Contradiction:

Improvesize of semiconductor chipVSAvoidhandling difficulty

Core Design Contradiction:

Volume of moving objectVSEase of operation

Solution Approach 1:

The patent introduces a protruding structure that extends the through-via electrode pad beyond the chip surface in the vertical dimension. This dimensional extension provides larger contact areas for bonding wires and facilitates handling without increasing the planar footprint of the miniaturized chip, thus resolving the contradiction between miniaturization and handling ease.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If the size of semiconductor chips and packages is reduced, then miniaturization is achieved, but manufacturing yield decreases

Engineering Contradiction:

Improvesize of semiconductor chipVSAvoidmanufacturing yield

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the through-via electrode structure by creating a protruding pad that extends beyond the chip surface. This parameter modification provides larger bonding areas and better mechanical interlocking, thereby improving manufacturing yield despite the overall miniaturization of the chip.

Inventive Principle:

Principle #35Parameter changes

3Volume of moving object

If the size of semiconductor chips and packages is reduced, then miniaturization is achieved, but manufacturing time increases

Engineering Contradiction:

Improvesize of semiconductor chipVSAvoidmanufacturing time

Core Design Contradiction:

Volume of moving objectVSLoss of time

Solution Approach 1:

The protruding structure of the through-via electrode pad is formed during the chip fabrication process itself, before packaging. This preliminary formation of the extended pad structure eliminates the need for additional post-packaging processing steps, thereby reducing overall manufacturing time despite the increased structural complexity.

Inventive Principle:

Principle #10Preliminary action

4Ease of operation

If the aspect ratio of through-via electrode is reduced, then handling is simplified, but additional processing steps are required

Engineering Contradiction:

ImprovehandlingVSAvoidprocessing steps

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the formation of the protruding pad structure with the existing through-via electrode fabrication process. By integrating the pad extension into the standard via formation steps using conventional photolithography and plating processes, the handling improvement is achieved without significantly increasing processing complexity.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the productivity and reliability of semiconductor packages by simplifying handling and reducing manufacturing time through improved layer formation and aspect ratio reduction.

Implementation Method 1

a method of forming these layers using chemical mechanical polishing to reduce the aspect ratio of the through-via electrode

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS9064941B2Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same

Publication Date: 2015.06.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.