Semiconductor Package Through-Via Exposure via Passivation
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Solution Overview
Problem
The miniaturization of semiconductor chips and packages has made them difficult to handle, leading to reduced manufacturing yield and increased production time, thereby decreasing productivity and reliability.
Innovation Solution
A method of manufacturing semiconductor packages involves preparing a parent substrate with package board parts, mounting chips with through-via electrodes, forming mold layers, and applying a passivation layer to expose and protect the electrodes, allowing for the stacking and connection of additional chips, and finally singulating the packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor chips and packages is reduced, then the functionality and integration density are improved, but the handling difficulty increases and manufacturing yield decreases
Solution Approach 1:
The chip structure is segmented into multiple functional layers including through-via electrodes, mold layers, and passivation layers. This segmentation allows each layer to be optimized independently for both miniaturization and manufacturing reliability, with larger support structures providing stability while smaller functional elements achieve high integration density
Solution Approach 2:
Mold layers are formed to cover and protect the back sides of chips before final assembly, and passivation layers are applied to protect through-via electrodes in advance. These preliminary protective actions prevent damage during handling and assembly, maintaining high manufacturing yield even as chip sizes are reduced
2Volume of moving object
If the size of semiconductor chips and packages is reduced, then the integration density is improved, but the handling difficulty increases and manufacturing time increases
Solution Approach 1:
Multiple protective and functional layers (mold layers, passivation layers, and interlayer insulating layers) are merged into an integrated multi-layer structure. This combination streamlines the manufacturing process by reducing the number of separate handling steps required, thereby decreasing manufacturing time while maintaining the reduced package size
Solution Approach 2:
The mold layers serve multiple functions simultaneously: they protect the back sides of chips, provide structural support, enable planarization for subsequent layer formation, and facilitate heat dissipation. This multi-functionality reduces the need for additional separate components and steps, improving manufacturing efficiency
3Reliability
If through-via electrodes are exposed for electrical connection, then the electrical connectivity is improved, but the chip structure becomes more vulnerable to damage
Solution Approach 1:
The passivation layer is selectively removed only at specific locations where through-via electrodes need to be exposed for electrical connections, while the rest of the chip structure remains protected. This localized approach maintains structural integrity in protected areas while enabling necessary electrical connectivity at exposed points
Solution Approach 2:
The chip structure employs composite material layers including passivation layers made of polymer materials or CVD insulating layers over the through-via electrodes. These composite structures provide both mechanical protection and electrical functionality, maintaining structural integrity while enabling electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the handling and manufacturing efficiency of semiconductor packages, increasing yield and productivity while enhancing reliability by allowing easier chip design and reducing production time.
Implementation Method 1
forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes
Implementation Method 2
etching the exposed back sides of the first chips to thin the first chips and to expose back sides of the through-via electrodes
Implementation Method 3
planarizing the first mold layer to expose the back sides of the first chips
Implementation Method 4
The first sub-passivation layer may include at least one chemical vapor deposition (CVD) insulating layer
Data Source
AI summary
A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.