Semiconductor Package Through Via Formation via Layered Substrate
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Solution Overview
Problem
The formation of through vias in semiconductor packages with mold resin core substrates is hindered by large inorganic fillers exposing on the hole wall surface, leading to surface roughness issues and incomplete connections due to differences in plating deposition speeds, which can result in voids and reduced reliability of electrical connections.
Innovation Solution
A semiconductor package design where a core substrate with a lower inorganic filler content and smaller grain diameter is used, covered by insulating layers with higher adhesiveness to metal, allowing for the formation of through vias that connect wiring layers across the substrate without exposing the core substrate's rough surface, enhancing the electroless plating process and electrolytic plating reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If mold resin with large inorganic fillers is used as core substrate material, then coefficient of thermal expansion matches semiconductor chip, but hole wall surface becomes rough with ridges and valleys
Solution Approach 1:
The core substrate is divided into two distinct layers: a lower layer containing large inorganic fillers for thermal expansion matching, and an upper layer with small inorganic fillers for smooth hole wall surfaces. This segmentation allows each layer to fulfill its specific function without compromise.
Solution Approach 2:
Different regions of the core substrate are assigned different filler characteristics. The lower layer (near semiconductor chip) uses large fillers for thermal management, while the upper layer (near through hole openings) uses small fillers to ensure smooth hole wall surfaces for reliable plating.
2Reliability
If through hole is formed in core substrate with large inorganic fillers, then electrical connection path is created, but plating deposition becomes incomplete with voids forming
Solution Approach 1:
The core substrate is segmented into layers with different filler sizes, ensuring that the region affecting plating quality (upper layer) has small fillers while the region affecting thermal matching (lower layer) has large fillers.
Solution Approach 2:
The upper layer of the core substrate specifically uses small inorganic fillers to ensure smooth hole wall surfaces in the plating region, while other regions may use different filler characteristics for their specific functions.
3Reliability
If insulating layer with high metal adhesiveness is added, then through via formation reliability improves, but device structure becomes more complex
Solution Approach 1:
The insulating layer is integrated with the core substrate structure, forming a unified component where the upper layer of the core substrate itself serves as the insulating layer with appropriate filler characteristics for both thermal management and smooth plating surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures the formation of high-quality through vias without defects, improving the reliability of electrical connections between the upper and lower sides of the core substrate by using insulating layers with adjusted filler content and grain size, facilitating better adhesion and plating processes.
Implementation Method 1
Adhesiveness of the first to third insulating layers to a metal is higher than adhesiveness of the core substrate to the metal
Implementation Method 2
enhancing the electroless plating process and electrolytic plating reliability
Data Source
AI summary
A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers.