Semiconductor Package Through-Via Layout for Fine-Pitch PoP Routing
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Solution Overview
Problem
The challenge in semiconductor packaging is to reduce the mounting area while maintaining high performance, particularly in package-on-package (PoP) structures, where existing solutions face limitations in designing efficient redistribution layers and through-vias for vertical electrical connections.
Innovation Solution
A semiconductor package design that includes a first redistribution structure with a buried semiconductor chip, an encapsulant, and a through-via with a pattern portion buried in the insulating layer and a via portion extending through the encapsulant, allowing for increased design freedom and reduced congestion in the redistribution layer by redistributing the via position without increasing layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through-via is formed to provide vertical electrical connection in a PoP structure, then electrical connectivity is achieved, but the mounting area increases and design freedom of redistribution layer is limited
Solution Approach 1:
The invention moves the connection terminal from the surface level to a buried position within the insulating layer. This dimensional change allows the through-via to be formed without occupying additional surface mounting area, as the connection terminal is integrated within the bulk of the insulating layer rather than requiring surface space
Solution Approach 2:
The connection terminal is nested within the insulating layer, with the insulating layer surrounding and embedding the connection terminal. This nesting approach allows the electrical connection structure to be contained within the existing package volume without increasing the overall mounting footprint
2Adaptability or versatility
If the via position is adjusted to improve redistribution layer design, then design freedom increases, but the layer thickness increases
Solution Approach 1:
The invention resolves the thickness issue by embedding the connection terminal within the insulating layer rather than extending it through the entire layer thickness. The connection terminal is positioned at a specific depth within the insulating layer, allowing via position adjustment without increasing overall layer thickness, as the connection is made at an intermediate level rather than requiring full thickness penetration
Data Source
AI summary
A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.