Semiconductor Package Through-Via Pad Planarization
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in achieving high structural stability and reliable electrical connections between stacked semiconductor chips, often resulting in defects and reduced reliability.
Innovation Solution
A method of fabricating a semiconductor package involves forming semiconductor chips with through vias that connect pads on opposite surfaces, using passivation layers with varying thicknesses to ensure flat contact surfaces, and employing hybrid bonding techniques to enhance structural stability and electrical connections between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging techniques are used to stack semiconductor chips, then chip integration density is improved, but structural stability and electrical connection reliability deteriorate
Solution Approach 1:
The patent applies preliminary action by forming through-vias and pad structures on the semiconductor substrate before stacking chips. The through-vias are pre-formed to extend from the front surface through the substrate to the back surface, and pad structures are pre-formed on both surfaces to ensure proper electrical alignment and connection before the stacking process occurs.
Solution Approach 2:
The patent uses an intermediary approach by introducing a passivation layer with controlled thickness variation over the pads. This passivation layer acts as a mediator that ensures flat contact surfaces between stacked chips while maintaining electrical connection through the pads, resolving the conflict between structural stability and electrical connectivity.
2Quantity of substance
If conventional packaging techniques are used to stack semiconductor chips, then chip integration density is improved, but structural stability deteriorates
Solution Approach 1:
The patent applies local quality by creating a passivation layer with spatially varying thickness. The passivation layer has greater thickness at certain locations compared to others, allowing different regions to serve different functions: thicker regions provide structural support and flat contact surfaces, while thinner regions allow electrical connections through the pads.
Solution Approach 2:
The patent performs preliminary planarization processes before stacking to ensure flat contact surfaces. The first planarization process is performed on the front surface pad structures, and the second planarization process is performed on the back surface pad structures, preparing the surfaces in advance for stable chip stacking.
3Manufacturing precision
If planarization processes are performed on pad layers, then flat contact surfaces are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the planarization process into multiple distinct steps: a first planarization process for the front surface pad layer, and a second planarization process for the back surface pad layer. This segmentation allows each planarization step to be optimized independently and performed at appropriate stages of fabrication, managing overall process complexity.
Solution Approach 2:
The patent performs planarization processes at preliminary stages before chip stacking. By completing the planarization of pad layers before the stacking process, the patent ensures flat contact surfaces are established in advance, avoiding the need for complex post-stacking adjustments or rework.
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.