Semiconductor Package Layout With Heat Dissipation Chip and Through Vias
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Solution Overview
Problem
As semiconductor packages are miniaturized and require higher performance, large capacity, and reliability, they face increasing power consumption and heat dissipation challenges, which affect their size and thermal management.
Innovation Solution
The semiconductor package design includes a redistribution substrate with multiple semiconductor chips, through vias, metal pads, adhesive layers, and heat dissipation chips, along with a sealant and connectors, to enhance structural reliability and heat dissipation, while maintaining a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are miniaturized to meet user demands for smaller and lighter electronic devices, then the size and weight of semiconductor packages are reduced, but heat dissipation capabilities deteriorate
Solution Approach 1:
The patent introduces a heat dissipation chip positioned beneath the semiconductor chip, utilizing the vertical dimension (Z-axis) for heat transfer. Heat is conducted from the semiconductor chip through the adhesive layer into the heat dissipation chip, which extends laterally to dissipate heat away from the package. This dimensional approach allows effective heat management in miniaturized packages without increasing horizontal footprint.
Solution Approach 2:
The patent employs an adhesive layer as an intermediary thermal interface material between the semiconductor chip and the heat dissipation chip. This intermediary layer facilitates efficient thermal conduction while maintaining mechanical bonding, enabling heat to be transferred from the heat-generating semiconductor chip to the heat-dissipating substrate without direct contact.
2Quantity of substance
If multiple semiconductor chips are stacked vertically to increase capacity, then the large capacity requirement is met, but structural reliability deteriorates due to increased stress and thermal expansion differences
Solution Approach 1:
The patent applies a uniform adhesive layer across all interfaces between stacked chips (semiconductor chip to heat dissipation chip, and between multiple semiconductor chips). This homogeneous adhesive bonding provides consistent mechanical support and stress distribution throughout the vertical stack, enhancing structural reliability while accommodating thermal expansion differences between dissimilar materials.
Solution Approach 2:
The adhesive layer serves as a cushioning element that pre-compensates for thermal expansion stresses that will occur during operation. By providing a compliant bonding interface before thermal cycling begins, the adhesive layer prevents stress concentration and potential delamination in the vertically stacked structure.
3Power
If power consumption is increased to achieve high performance, then the performance of semiconductor packages is improved, but heat dissipation challenges worsen
Solution Approach 1:
The patent converts the harmful effect of high power consumption (excessive heat generation) into a beneficial thermal management system. The heat dissipation chip, positioned beneath the semiconductor chip, captures the waste heat generated by high-power operation and conducts it laterally to designated heat dissipation regions, transforming the harmful thermal byproduct into a manageable and even useful thermal flow pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the structural reliability and heat dissipation capabilities of semiconductor packages, addressing the challenges of increased power consumption and thermal management, thereby enhancing their performance and reliability.
Implementation Method 1
a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction
Implementation Method 2
a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip
Implementation Method 3
the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction
Data Source
AI summary
Provided is a semiconductor package including a redistribution substrate, a first semiconductor chip on the redistribution substrate, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in a horizontal direction, a third semiconductor chip on the second semiconductor chip, and a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, wherein the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction, and wherein a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip.