Semiconductor Package Through-Via Interconnects for IR Drop Reduction
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Solution Overview
Problem
Existing ball grid array (BGA) semiconductor packages face issues with IR drop effects due to long connection paths between central and peripheral input/output pads, leading to performance degradation and increased complexity in chip fabrication.
Innovation Solution
The semiconductor package design includes a circuit board with through holes and a stair-like portion, allowing input/output pads to be placed on both the central and peripheral edges of the semiconductor chip, with conductive connections spanning through these holes to reduce IR drop effects and simplify interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If input/output pads are placed only on peripheral edges of the semiconductor chip, then the chip fabrication is simpler, but the connection paths become long causing significant IR drop effects
Solution Approach 1:
The patent transitions from a two-dimensional peripheral pad arrangement to a three-dimensional configuration by placing pads on both the front surface (central region) and back surface of the chip. This dimensional change allows current to flow through shorter vertical and lateral paths via through-chip vias, significantly reducing IR drop effects while maintaining fabrication simplicity.
Solution Approach 2:
The patent segments the pad arrangement into multiple groups located at different positions (front surface central region, back surface, and peripheral edges). This segmentation creates multiple independent current paths, reducing the overall resistance and IR drop effects compared to a single peripheral arrangement.
2Reliability
If input/output pads are placed on both central and peripheral regions, then IR drop effects are reduced, but the interconnect structure becomes more complex
Solution Approach 1:
The back surface of the chip serves multiple functions: it provides additional pad placement area for reducing IR drop effects, and simultaneously acts as an external connection surface for wire bonds or other interconnect structures. This multi-functionality reduces the need for separate internal interconnect layers, thereby limiting the increase in overall structure complexity.
3Area of stationary object
If wire loops are made longer to connect peripheral pads, then the chip area can be reduced, but the package performance degrades due to increased inductance and resistance
Solution Approach 1:
The patent uses through-chip vias to create vertical current paths, transforming the current flow from purely lateral (two-dimensional) to include vertical components (three-dimensional). This allows pad connections with minimal lateral wire loop lengths, reducing inductance and resistance while maintaining compact chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces IR drop effects, simplifies chip fabrication, and enables more flexible and compact IC designs by providing shorter wire loops and increased pad density, thereby enhancing package performance.
Implementation Method 1
The heat spreading layer is formed over the semiconductor chip
Data Source
AI summary
A semiconductor package includes a circuit board, a semiconductor chip, a heat spreading layer, an encapsulant layer, a plurality of conductive connections, and a plurality of solder balls. The circuit board includes opposite first and second surfaces and a plurality of through holes. The semiconductor chip is formed over a center portion of the first surface of the circuit board, having an active surface facing the circuit board. The heat spreading layer is formed over the semiconductor chip. The encapsulant layer is formed over the circuit board, covering heat spreading layer, the semiconductor chip, and the circuit board. The plurality of conductive connections respectively passes through the through holes and electrically connecting the semiconductor chip with the circuit board. The plurality of solder balls are formed over the second surface of the circuit board.