Semiconductor Package With Through Vias For Signal Quality
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization and signal quality due to the need for bonding wires, which increase noise and power consumption, and make it difficult to integrate a controller chip with multiple memory chips in a single package while maintaining effective heat radiation and inspection capabilities.
Innovation Solution
The semiconductor package design includes a package board with multiple NAND chips stacked in the thickness direction, a controller chip disposed between the board and the NAND chips, and through vias that penetrate the NAND chips to connect them electrically to the controller chip, eliminating the need for bonding wires and enhancing signal quality and heat radiation through strategically placed thicker vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect memory chips and controller chip, then electrical connection is achieved, but noise increases and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the bonding wires from the package structure, replacing them with a direct PCB mounting approach where memory chips and controller chip are mounted on opposite sides of the PCB and connected through PCB traces, thereby removing the source of noise and excess power consumption
Solution Approach 2:
The patent replaces the mechanical bonding wire connection system with an electrical connection system using PCB traces, substituting the physical wire bonding mechanism with a printed circuit board-based electrical pathway that reduces noise and power loss
2Volume of moving object
If multiple memory chips and controller chip are integrated in a single package, then package size is reduced, but heat radiation becomes difficult
Solution Approach 1:
The patent segments the integrated package into two separate PCBs - a first PCB for mounting memory chips and a second PCB for mounting the controller chip, allowing each component to be thermally managed independently while maintaining a compact overall structure through the stacking configuration
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacking configuration where memory chips and controller chip are mounted on opposite sides of the PCB and connected through vertical vias, enabling compact packaging while improving heat dissipation through increased surface area exposure
3Device complexity
If controller chip is sealed with NAND chips in the package, then integration is achieved, but inspection of controller chip becomes difficult
Solution Approach 1:
The patent segments the integrated assembly into separable components mounted on opposite sides of the PCB, allowing the controller chip to be electrically connected to memory chips while remaining physically accessible for inspection and replacement without requiring complete disassembly of the package
4Reliability
If bonding wires are used for connection, then electrical connection is established, but device complexity increases
Solution Approach 1:
The patent extracts and removes the bonding wire connection structure entirely, replacing it with a simplified PCB trace-based electrical connection system that reduces structural complexity while maintaining reliable electrical connectivity between components
Solution Approach 2:
The patent changes the connection parameter from wire-based physical bonding to trace-based electrical routing, fundamentally altering the connection methodology to achieve simpler device structure with equivalent or superior electrical performance
Data Source
AI summary
A semiconductor package includes a board, a plurality of semiconductor memory chips, a controller chip, and a sealing resin portion. The plurality of semiconductor memory chips are stacked in a thickness direction of the board. The controller chip is disposed between the board and the plurality of semiconductor memory chips or on a side of the plurality of semiconductor chips opposite to the board. The sealing resin portion seals the plurality of semiconductor memory chips and the controller chip. The plurality of semiconductor memory chips include at least one through via that penetrates one or more semiconductor memory chips of the plurality of semiconductor memory chips in the thickness direction of the board to be connected to the controller chip.