Semiconductor Package Top Testing Contacts
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Solution Overview
Problem
Current semiconductor packages face challenges in testability and size optimization, as dedicated testing contacts often occupy valuable space on the bottom surface, hindering the placement of interface contacts necessary for regular operation and increasing the package footprint.
Innovation Solution
The semiconductor package design relocates dedicated testing contacts to the top surface, utilizing conductive mediums and interposers to provide electrical connections, thereby freeing up space on the bottom surface for interface contacts, reducing the package size and enhancing functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If dedicated testing contacts are provided on the bottom surface of the semiconductor package, then testability is improved, but the package footprint increases and space for interface contacts is reduced
Solution Approach 1:
The patent applies dimensionality change by moving dedicated testing contacts from the bottom surface (2D plane) to the sidewall (3D vertical dimension) of the package. This allows testing functionality to be achieved without occupying additional bottom surface area, thereby resolving the contradiction between improved testability and reduced package footprint.
Solution Approach 2:
The patent segments the package structure into distinct functional zones: interface contacts remain on the bottom surface for operational connectivity, while dedicated testing contacts are separated and placed on the sidewall for testing purposes. This segmentation allows both functions to coexist without competing for the same spatial resources.
2Difficulty of detecting and measuring
If dedicated testing contacts are provided on the bottom surface of the semiconductor package, then testability is improved, but the number of interface contacts that can be placed is reduced
Solution Approach 1:
By relocating dedicated testing contacts to the sidewall dimension, the patent frees up bottom surface space that can then be utilized for additional interface contacts, thereby increasing the quantity of interface contacts without compromising testability.
Solution Approach 2:
The separation of testing contacts from the bottom surface allows the bottom surface to be dedicated entirely to interface contacts, maximizing their quantity while maintaining independent testing capability through sidewall contacts.
3Area of stationary object
If the package footprint is reduced to optimize size, then space efficiency is improved, but testability may be compromised
Solution Approach 1:
The patent maintains compact package footprint by utilizing the vertical sidewall dimension for testing contacts rather than expanding the bottom surface area. This allows small footprint packages to retain full testing capability without requiring additional bottom surface space.
Data Source
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AI summary
An exemplary implementation of the present disclosure includes a testable semiconductor package (100) that includes an active die (102) having interface contacts (112a-112c) and dedicated testing contacts (114a, 114b). An interposer (104) is situated adjacent a bottom surface (116a) of the active die (102), the interposer (104) providing electrical connections between the interface contacts (112a-112c) and a bottom surface (118a) of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts (114a, 114b) and a top surface (118b) of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection (108a, 108b), which may include a solder ball.