Semiconductor Package Conductive Trace Layout Without Recesses
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Solution Overview
Problem
Conventional semiconductor packages face issues with incomplete conductive trace structures due to recesses, leading to reduced strength and connectivity challenges, which affect transmission speed and reliability.
Innovation Solution
A semiconductor package design featuring a substrate with a first and second insulation layer, where the second insulation layer has through holes extending to conductive pads, and a conductive trace connected without recesses, ensuring both surfaces are at the same level, enhancing structural integrity and reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the conductive trace conforms to the shape of the through hole to form a recess, then the conductive trace can be connected to the conductive component, but the structural strength is reduced and the structure becomes incomplete
Solution Approach 1:
The patent introduces a filling layer that fills the recess formed by the conductive trace conforming to the through hole shape. This adds a third dimension (vertical filling) to resolve the structural weakness caused by the recess, transforming the incomplete trace structure into a complete, strength-enhanced structure while maintaining the original connection approach.
2Productivity
If conventional semiconductor package structures are used, then manufacturing is simpler, but transmission speed is limited and connectivity is incomplete
Solution Approach 1:
The patent employs composite material structures by combining the conductive trace material with a filling layer material. This composite approach creates a more reliable and complete connectivity structure that enhances transmission speed while ensuring structural integrity, overcoming the limitations of conventional single-material trace designs.
3Reliability
If the conductive trace forms a recess to connect with the conductive component, then electrical connection is achieved, but parasitic resistance increases and transmission speed decreases
Solution Approach 1:
The filling layer acts as an intermediary between the conductive trace and the through hole wall. This intermediary structure provides additional conductive pathways and reduces the effective length of the recess, thereby lowering parasitic resistance while maintaining reliable electrical connection and enabling faster transmission.
Data Source
AI summary
A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.