Semiconductor Package Trenches for Heat Dissipation and Mold Control

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving miniaturization, high performance, and reliability while maintaining a compact and efficient structure for stacked semiconductor chips.

Innovation Solution

A semiconductor package design featuring a semiconductor chip with concave trenches on its surface, allowing partial exposure and forming distinct areas to manage heat dissipation and molding material flow, combined with a redistribution layer and molding layer to enhance connectivity and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor chips are stacked in multiple levels for miniaturization, then the package size is reduced and capacity is increased, but heat dissipation becomes more difficult and reliability decreases

Engineering Contradiction:

Improvepackage sizeVSAvoidheat dissipation

Core Design Contradiction:

Volume of moving objectVSTemperature

Solution Approach 1:

The top surface of the semiconductor chip is segmented into multiple functional areas: a first area for heat dissipation, a second area for molding material flow, and a third area for electrical connection. This segmentation allows each area to perform its specific function optimally, with the first area directly exposed to air for efficient heat dissipation while the other areas remain protected by the molding layer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the chip top surface are given different properties: the first area has direct air exposure for heat dissipation, the second area allows molding material infiltration for structural support, and the third area maintains electrical connectivity. This local differentiation resolves the contradiction by allowing heat dissipation in specific zones without compromising overall package integrity.

Inventive Principle:

Principle #3Local quality

2Temperature

If the semiconductor chip surface is fully exposed for heat dissipation, then heat dissipation efficiency is improved, but molding material may intrude into critical areas causing reliability issues

Engineering Contradiction:

Improveheat dissipation efficiencyVSAvoidmolding material intrusion prevention

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

The chip top surface is divided into distinct zones: the first area is exposed for heat dissipation, while the second and third areas are protected by the molding layer to prevent material intrusion and maintain electrical connections. This segmentation allows simultaneous achievement of heat dissipation and reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different surface regions have different exposure levels: the first area is fully exposed to air for heat dissipation, the second area allows controlled molding material infiltration for structural support, and the third area remains protected for electrical connectivity. This local quality differentiation resolves the contradiction between heat dissipation and reliability.

Inventive Principle:

Principle #3Local quality

3Temperature

If trenches are formed around the periphery of the semiconductor chip, then molding material flow is controlled and heat dissipation is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveheat dissipation and molding material flow controlVSAvoidtrench formation process

Core Design Contradiction:

TemperatureVSEase of manufacture

Solution Approach 1:

The peripheral region of the chip is segmented into multiple trenches (first, second, and third trenches) at different locations and depths. These trenches create distinct flow paths for molding material while maintaining heat dissipation channels, achieving functional control without excessive manufacturing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple trenches are nested or arranged in a hierarchical pattern around the chip periphery, with inner trenches closer to the chip center and outer trenches near the edges. This nested arrangement efficiently controls molding material flow through multiple barriers while maintaining heat dissipation pathways, balancing manufacturing complexity with functional performance.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250343156A1Semiconductor package and semiconductor package manufacturing method

Publication Date: 2025.11.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a semiconductor substrate on which a redistribution layer is formed; a semiconductor chip having a first surface that is disposed opposite the semiconductor substrate; a bump connecting the semiconductor chip to the redistribution layer; and a molding layer at least partially surrounding the semiconductor chip, wherein the first surface of the semiconductor chip includes: a trench area where one or more trenches, which have a closed loop shape and are concave, are positioned; a first area surrounded by the trench area; and a second area positioned on an outer side of the trench area, and the first surface of the semiconductor chip is exposed to an outside of the molding layer at least through the first area.