Semiconductor Package With Through Silicon Vias and Localized Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in achieving high manufacturability and performance for sensor chips, particularly in creating reliable and flexible packaging solutions that optimize wafer-level integration and interconnects.
Innovation Solution
The proposed semiconductor package and manufacturing method involve a plurality of chips with sensing areas, through silicon vias, insulators, and encapsulants, where through silicon vias are formed in the chips to connect conductive pads, and a circuit structure is formed on the back surfaces to redistribute signals, with encapsulants laterally encapsulating the chips to enhance integration and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used for sensor chips, then manufacturing process is simpler, but operating performance and sensing capabilities are degraded
Solution Approach 1:
The sensor chip is divided into distinct functional regions: a sensing area with through-holes for target object interaction, an active surface with conductive pads, and a back surface with circuit structures. This segmentation allows the sensing area to remain exposed for optimal performance while other areas are packaged, resolving the contradiction between exposure and protection.
Solution Approach 2:
Different regions of the chip receive different treatments: the sensing area remains exposed with through-holes for sensing functionality, while the back surface and edges are encapsulated for protection. The insulator is selectively applied to specific regions, providing local protection without compromising overall sensing performance.
2Reliability
If sensor chips are exposed for sensing, then sensing capabilities are improved, but chips become vulnerable to damage during assembly
Solution Approach 1:
The insulator is applied selectively to protect specific vulnerable regions (back surface and edges) while leaving the sensing area exposed. This localized protection approach maintains sensing capabilities while providing damage protection during assembly through the insulator layer and encapsulant.
Solution Approach 2:
The insulator is applied to the chip before packaging, providing a protective cushioning layer that prevents damage during subsequent assembly processes. The encapsulant further provides mechanical support and protection, cushioning the exposed sensing area from external stresses.
3Reliability
If through silicon vias are formed to connect conductive pads, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
Through-holes are formed and conductive pads are established on the active surface before the chip is packaged. This preliminary action allows electrical connectivity to be established early in the manufacturing process, simplifying subsequent packaging steps and improving overall manufacturing efficiency despite the added complexity of via formation.
Data Source
AI summary
A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.